EtherCAT Master主站同步时钟技术资料

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2024年7月13日发(作者：)

EtherCAT Products family

Master Synchronization with Distributed Clock

Distributed Clocks Feature

1. Distributed Clocks Feature

Distributed Clocks (DC) feature in the EtherCAT® has been introduced to perform synchronization

of the master and all slave devices in the bus.

In general it works in the following way: when the feature is enabled, the master or a first DC-

capable slave in the network is configured to become a reference clock. Then the time of the

reference clock is propagated along the network to all slaves through the EtherCAT master.

1.1. DC slave as a reference clock

When the first DC slave is used as a reference clock, the EtherCAT Master sends ARMW in cycles

to read the bus time from the appropriate register of the clock master and write this value in the

corresponding registers of the rest DC slaves.

1.2. EtherCAT master as a reference clock

In this case the master sends the BRW command in order to propagate its local time among

the corresponding DC slaves. Update of local times in the DC-capable slaves is performed with

a controller integrated in their ESC (EtherCAT Slave Controller).

In both cases it is necessary to compensate delays in transporting the EtherCAT frames emerging

between particular slaves, so as to keep up with the requested accuracy that may range even

below 1us for the slaves clocks. It is provided in the following way: for each slave the time between

the frame departure and frame arrival is measured at each connected port. Then the master

computes the delays between the slaves and writes the corresponding compensation values into

the appropriated register of the ESC.

The ESC controller's DC unit provides two digital output signals, SYNC0 and SYNC1.

Based on the bus time, these SYNC pulses, whose frequency generally corresponds to the EtherCAT

bus clock, are generated. For example, if the EtherCAT master sends the cyclical I/O data at a 500 us

rate, as a rule the SYNC pulse frequency will be set to 2 kHz. On the one hand, these SYNC signals are

available as a digital output signal (e.g. to activate the slave hardware components) on the slave side

and, on the other hand, as an interrupt source for the slave software.

Document version 1.0

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EtherCAT Products family

Master Synchronization with Distributed Clock

Distributed Clocks Feature

Taking into account the aforementioned, it is obvious that all slaves have to be provided with the

new data before the SYNC pulse is released, see picture below Thus a minimum time lag between

the arrival of new cyclical I/O data and the SYNC pulse must be guaranteed to ensure this data

update.

The local apolicaton is started with a local timer. The local timer is shifted to the DC base Time by

the sum of the tollowmg times:

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