UVM实战学习笔记

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2.2 the test bench only have driver

2.2.1 init sample

2.2.2 add factory

2.2.3 add objection

UVM will use “Objection” ot control the close of the test bench. in every phase, UVM will check the “Obection” raised,
if"raise_objection", which will wait the objection be droped <drop_objecton>; or not, finish the phase right now’
raise_objection/drop_objection will be match;
raise_objection must be in the place of before the first time consume sentense in main_phase

eg:
 @(posedge top.clk)
       "$display" is not consume the time 

simulation time is "$time" printing time
running time is the tese case consume cpu time

2.2.4 add virtual interface

the virtual interface will improve the reusability and portability of the code
we can use marco to define the top_tb
eg:"define TOP top_tb
this is useful when the “top.clk” be changed to ‘top.clk_inst.clk’, we can only modify the marco define
in class can not use"interface"like"my_if output_if(clk,rst_n);’only can use "virtual interface’
"config_db’has set/ get operations, set mean send mails and get means receive mails
build_phase: like mainphase is a uvM internal phase, when uvm start, the build phase will be called auto
build_phase is executed after new function, before main_phase function
buildphase is function phase and not consume simulation time which will be executed in the time of zerolstime functi
main phase is task phase build_phase must be call 'super.build_phaseas the parent build phase must be executed some set/get operation and se
uvm_config_db#(virtual my_if)isaparameterclass,and the parameter is send mail type, such as virtual my_if,
if you want to send a value to my_driver’s var, you can do like this:

      initial begin
          uvm_config_db#(int)::set(null,"uvm_test_top","var"，100); 
      end

2.3 add component to test bench

In the 2.2, all the operation is based on the singal, now we will import the reference model, monitor, scoreboard, and other s test bench components. All of the components will transform the information based on the transaction

2.3.1 add transaction

all of the transaction will be extended from uvm_sequence item uvm_component utils/uvm object utils: factory
my driver is always exitence on the whole simulation, but the my transaction is differenct, which life is produced in one time of the simulation passed by driver and processed by reference mode; at the end compared by the scoreboard
so like the 'mytransaction’which extends from uvm_object or uvm_object extended class, will use the 'uvm object utils’marco to implement. uvm_sequence_item’s ancestor is ‘uvm_object’#

2.3.2 add env

uvm env: a container, driver. monitor,reference model, scoreboad will be implemented in it, when calling ‘runt test’ the params will not be my driver but be the container, which will let the uvM automatic to create the container instance. uvm env:the build phase will be executed from tree root to tree leaves,

2.3.3 add monitor

monitor: monitor the dut component
driver:format the transaction data to the DUT port data and driver to DUT,
monitor: collect the DuT port data, and format to transaction and transferto thelater flow component like: reference model, scoreboard;

2.3.4 add agent

include monitor and driver
UVM tree must be built in ‘build_phase’, if instance a component after ‘build_phase’, there will be a build error:

UVM_FATAL@0:iagt [ILLCRT] It is illegal to create a component ...

there will be two ways to instance the driver and monitor:

1. first in the agent 'build phase’
2. second in the agent new function

the second way will be a problem such as: we can not set the state for 'is active’in the envclass’s 'build_phase’set the value will be useless so the i agt & o agt will all be ‘is_active = UVM ACTIVE’
howto fix:use config db to set the value in my_agent before instance the i agt and o_agt

eg.

uvm config db#(uvm active passive enum)::set(this,"i agt", "is_active", UVM ACTIVE); 
uvm_config_db#(uvm_active_passive_enum)::set(this, "o_agt","is_active", UVM PASSIVE); 
i_agt = my_agent::type_id::create("i agt",this); 
o_agt = my agent::type id::create("o agt", this);

2.3.5 add reference model

TLM(TransactionLevelModeling:conmunication with transaction between component how to implement the comunication ?

1. how to send data?
2. how to receive data?
3. how to connect send and receive port

send data:
H haa many methods to send data, one of them is"uvm_analysis_port"which is parameter class, and the parameter is the data type to send

reveive data:
uenveas many methods to reveive data, one of them is "uvm_blocking_get_port"which is parameter class, and the parameter is the data type to recevie

connect port:
UVMCuse rtim_tlm_analysis_fifo’connect the send&receive port,whihc is parameter class, and the parameter is the transaction type
connect_phase is like build phase &main_phase, which is internal uvM build phase, and will be executed after build_phase the differece between build phase and connectphase is the build sequence:
build phase: from root to leaf connect_phase: from leaf to root

eg :
driver/monitor ·> agent > env <connect_phase> 

why need fifo?
analysis_port is blocking , ap.write will return after be called and will not wait for the data be receive.
when write is called, blocking_getport is busy and not ready for receive data, this is need a tmp place for store the write transaction.

2.3.6 add scoreboard

scoreboard has two input data to be compared: one from referene model, one from o agt monitor
reference model : get from 'exp_port.o_agt monitro : get from ‘act_port’
in main phase fork two process,

one for process expport data, when reveive data, put data to expect_queue;

another for process act port data, this is DUT output data, when get this data, pop data from expect queue which gets from exp port, calling my transaction my compare function. we must make sure the exp port get data berore act port get data. as but has latency, and the model is high programing language which doe not have latency. so this can be make sure.

2.3.7 add field automation

2.4 add sequence

2.4.1 add sequencer

2.4.2 add sequence

sequence has two parts:

sequence : not be a part of test bench
sequencer:produce motivate and the driver only receive the transaction

inch2.3 the motivate is produce by driver, but in the formal UVM testbech, driver only drive transaction and not produce transaction
sequence: uvm object like mytransaction, sequence has the life period, which is longer than mytransaction. when all the transactions in the sequece is sent, the life is over
so the sequence will be register by ‘uvm_object utils’

all the sequence extends form uvm sequence and define the produce data type
all the sequence has body task, when sequence start, the body task will be execute automatically
sequencer:uvm component
uvm_do:this is the most import marco in the uvm, it was used for:

1. create my_tansaction instance
2. random the transaction instance
3. send it to the sequencer

if do not use the uvm_do, use ‘start_item’/'finish_item’ to produce transaction
before sequence send a transaction to sequencer

1. sequence must send a request to sequencer,
2. sequencer put eht request to the arbitration queue for the sequencer , must do :
   check the arbitration queue for the sequence sended transaction request
   check wheather the driver request the transaction

if the arbitration queue has transaction sendrequest, but driver doesnot request transaction. the sequencer will wait for the driver until the driver request the transa and then the sequencer approve the sequence request, sequenceget the response about requestapporve, produce a transaction and send to sequencer, sequencer send it to driver

if the arbitration queue has not the transaction send reauest. but driver senda reouest transaction. so the seauencer will wait for the seouence state. until the seouend a request, the sequencer approver the request, sequence produce a transaction send to sequencer, and the dirver get the transaction.

if the arbitration queue has the sequence request and at the same time the driver request a newtransaction to the sequencer, so the sequencer approve the request, the transactionproducedbythesequencesend to sequencer, and the driver will get the transaction

the driver how to requset the transaction?
the uvm driver has the member ‘seq item port’
the uvm_sequencer hsa the member ‘seq_item_export’
the tow build a path ,the send transcation type if defined when define the class my_sequencer and the class my_driver
get_next_item/item_done

my driver.sv#main_phase(...)
while(1) begin
seq item port.get next_item(req); // sequence 
drive one pkt(req); //transaction
seq_item port.item_done(); // sequence //why? 
end

while(1) the driver only charge of the drive transaction and not produce, so if there is a transaction, it will be drive.>get next_item/item_done: which is a shake hands mechanism to enhance the reliability

when driver use get next item to get a transaction, the sequencer will keep a cache for the trasaction; when it happened that the sequencer send the transaction but the driver does not get it, the sequencer will send it again.

when diver calls get next item next time before, item done is called, so the sequencer will make sure the driver had received the transaction. so the sequencer will delete the cache of the transaction.

when use uvm do in sequence send transaction to sequencer, when it return?
uvmdo marco produce a transaction then senditto sequencer, and driver get the transaction,
the uvm do will not do calling again but waiting until the drive return the item done singal
this is the end of the uvm do.

now senquence send transaction to sequencer?
when define sequence, we just stat the sequence in one of component’s<eg: my_sequencer,my_env> main phase…

    eg1:start it in my env.sv
    src/ch2/section2.4/2.4.2/my_env.sv
    48 task my_env::main_phase(uvm phase phase);
    49     my sequence seq;
    50     phase.raise_objection(this);
    51      seq = my_sequence::type_id::create("seq");
    52      seq.start(i agt.sqr);
    53      phase.drop objection(this);
    54 endtask

 1. create 'my_squence’instance seq
 2. call the start function: the paramters is a sequencer point, if not set the point, the sequence will not know who to send the produced transaction 

Note: in uvM objection is beside the sequence, so only the seqence come up, the objection can be raise and drop. when the sequence’s transaction is all
send to sequencer, the simulator is over.

     eg2: start it in sequencer
     task my_sequencer::main_phase(uvm_phase phase);
          my_sequence seq;
          phase.raise_objection(this);
          seq = my_sequence::type_id::create("seq"); s
          eq.start(this);
          phase.drop_objection(this); 
     endtask

the difference of the start in sequencer and themy_envis the parameter, one is ‘i agt.sqr’, another is 'this

2.4.3 default_sequence

in the 24.2, we start he sequence in my env’s mainphase. but in project, we will use default sequence to start sequence; this is veryeasy to use default_sequence. only set in one of the component’build_phase like below:
eg:src/ch2/section2.4/2.4.3/my_env.sv

virtual function void build phase(uvm_phase phase);
super.build phase(phase);
uvm config db#(uvm object wrapper)::set(this,
"iagt.sqr.main_phase",// my_env is the uvm_test_top, so the path is    
                                        //agent.sequencer.main_phase"default sequence",
my_sequence::type_id::get());
endfunction

eg:start it in top_tb

module top tb;...
initial begin
uvm_config_db#(uvm_object wrapper)::set(null,// toptb is not a class, so this is null,
"uvm_test_top.i_agt.sqr.main_phase",// here is root of UVM tree path"default sequence",
my_sequence::type_id::get())

uvm config db will come up set/get, but the defaultsequence donot need toget in the sequencer, as the uvm have done this mechanism
default sequence need 'raise/drop’operation or not? when?

not need, in the uvm sequence base class, there is aattribute’staring_phase"which is a type of ‘uvm_phase’, when the sequencer start the default sequence which will do automaticlly like below:

task my sequencer::main_phase(uvm_phase phase);
seq.starting_phase = phase; 
seq.start(this);
endtask

so,we can use starting_phase start/drop objection in sequence

2.5 add test cases

2.5.1 add base_test

2.5.2 start the test

3.1 uvm component extends uvm_object

uvm component property:

set parent parameter when new to component the uvm tree
phase auto execute

3.2 field automation marco

3.3 field automation with if

3.4 UVM print info control

3.4.1 print info verbosity max level

typedef enum 
 {
    UVM_NONE=0, 
    UVM LOW =100, 
    UVM MEDIUM = 200, 
    UVM HIGH =300, 
    UVM FULL=400,
    UVM DEBUG =500
   }uvm verbosity;

default is UvM MEDIUM.

// connect phase
env.i agt.drv.set report verbosity level(UVM HIGH);
//env.i_agt.drv.set_report_id_verbosity("my_driver",UVM HIGH);
// env.i agt.set report_id verbosity_hier(UVM_HIGH);
//env.i_agt.set_report_id_verbosity_hier("my_monitor",UVM_HIGH);
// <sim command> +UVM VERBOSITY=UVM HIGH OR <sim command> +UVM VERBOSITY=HIGH

3.4.2 print info severity override

// connect phase
env.i agt.drv.set_report_severity_override(UVM WARNING, UVM ERROR);
//env.i agt.drv.set_report_severity_override(UVM WARNING, "my driver", UVM HIGH);
//SIM_COMMAND +uvm_setseverity="uvm_testtop.env.i agt.drv,my_driver,UVM WARNING,UVM_ERROR"

3.4.3 end simulator for max count error

// build phase
set_reportmax_quit_count(5);//get max_quit count :if return value is e which means the simulator will not be guit
//+UM MAXQUIT_COUNT=6,
//6is max quit error count, and no means the numbers will not be overrideed

3.4.4 set count target

connect_phase(uvm phase phase);
    set report max quit count(5);
    env.agt.arvset_report _severityaction(UVMWARNING，UVMDISPLAYIUVM_COUNT);
    // set evn.iagt.drv 'S UVM WARNING to count 
    env.i agt.drv.set report severityactionhier(UVM_WARNING,UVM_DAIPLAY | UVM_COUNT);// recursive calling
    // remove UVM ERROR from count target
    // env.i agt.drv.set_report_severity_ation(UVM_ERROR, UVM_DISPLAY) ;
    fro targetid, add'mydrv"all info to count,include :UM_INFO, UVM_WARNING, UVM_ERROR, UVM_FATAL
    //env.i agt.drv.set_report_id_action("my_drv", UVM_DISPLAY | UVM_COUNT);
    // env.i agt.drv.set_report_idatcion_hier("my_drv",UVM_DISPLAY | UVM_COUNT);// recursive calling
    // env.iagt.drv.set_report_severity_idaction(UVM WARNING,"my_driver",UVM_DISPLAY | UVM_COUNT);
    // set severity and id
    // env.i agt.drv.set report severityid action_hier(UVM_WARNING,"my_driver"，UVM_DISPLAYUVM_COUNT);
    // set severity and id , recursive calling
    // <sim command> +uvm_set_action=<comp>,<id>,<severity>,<action>
    //<sim command>+uvm_setaction="uvm_test_top.env.i_agt.drv,my_driver,UVM_NG,UVM_DISPLAY|UVM_COUNT"
    //<simcomman>+uvm_setaction="uvm_test_top.env.i_agt.drV,_ALL_,UVM_WARNING,UVM_DISPLAY|UVM_COUNT" // all id

3 4.5 set break point

connect _hase(uvm phase phase);
    set_report_max_quit_count(5);
    env.i agt.drv.setreport severity_action(UVM_WARNING,UVM_DISPLAY |UVM_STOP);
    // set break point
    env.iagt.drv.set_report_severity_action_hier(UVM WARNING,UVM DAIPLAY|UVM_STOP);
    // recursive calling
    // frotarget id, add'my_drv'all info to count, include :UVM INFO, UVM WARNING, UVM ERROR, UVM_FATAL
    // env.iagt.drv.set_report_id action("my_drv", UVM_DISPLAY | UVM STOP);
    //env.i agt.drv.set_report id_atcion_hier("mydrv",UVM DISPLAY|UVM STOP);// recursive calling
    //env.i_agt.drv.set_report_severity_idaction(UVM WARNING,"my driver",UVM DISPLAY |UVM STOP);// set severity and id
    // env.i agt.drv.set_report_severity_id actionhier(UVMWARNING,"my driver",UVM DISPLAYUVM STOP);// set severity and id, recursive calling
    //<sim command> +uvm set action=<comp>,<id>,<severity>,<action>
    //<sim command> +uvm_setaction="uvm_test_top.env.i agt.drv,my driver,UVM NG,UVM DISPLAY|UVM STOP"
    // <sim command>+uvm_set_action="um_test_top.env.i_agt.drV,_ALL_,UVM_WARNING,UVM_DISPLAY|UVM_STOP" // all id 
endfunction

3.4.6 output loginfo to file

set info by severity
///remote/aig/users/jianli/uvm_project/src/ch3/section3.4/3.4.6/severity
set info by id
// /remote/aig/users/jianli/uvm_project/src/ch3/section3.4/3.4.6/id
set info by id & severity
///remote/aig/users/jianli/uvm_project/src/ch3/section3.4/3.4.6/id severity

3.4.7 control action

typedef enum {
    UVM NO ACTION ='b000000, 
    UVM DISPLAY ='b000001, 
    UVM DISPLAY ='b000001,
    UVM LOG ='b000010,
    UVM COUNT ='b000100.
    UVM EXIT ='b001000,
    UVM CALL HOOK ='b010000, 
    UVM STOP ='b100000 } uvm action type;

3.5 config_db mechanism

3.5.1 UVM path

1.uvm patth :$display(“*s”,get_full_name());-> uvm_test_top.env.i_agt.drv <in my_driver
2. path & hierarchy

drv = my_driver::type_id::create("driver"); //1 
drv = my_driver::type_id::create("drv"); //2

for the 1 and2the hierarchy is same :env.i_agt.drv but the path of 1 is env.i_agt.driver
uvm top: _top, this is not display in path
uvm_test top: the name is "uvm_testtop"which is automiclly set when uvM executes the "runtest’
NOTE:variable name and instance name must be same when coding

3.5.2 config_db set/get params

uvm config db#(int)::set(this, "env.i_agt.drv","pre_num",100);
    >paraml&param2 joint the target path <the path must be same can receive mail>
    > paraml must be a uvm_component instance point
    > param2 muat be relative path for the paraml
    >param3 is a flag, pointed which member the values will be send for the target
    > param4 is the set value
uvm config_db#(int)::get(this, "","pre_num", pre_num);
    >param1&param2 joint the target path <the path must be same can receive mail>
    >paraml must be a uvm component instance point
    > param2 muat be relative path for the paraml
    > param3 is the same as the set param3
    > param4 is the set value valuable
-Note:if the paraml is set 'this', the param2 can ben set to NULL, like ""

Note:in ch02, the top_tp use the config_db shet the virtual interface, the paraml is null, in the situation, the uvm will
set the params to “uvm root::get()” which is uvm top automiclly

initial begin
uvm_configdb#(virtual my_if)::set(null,"uvm_test_top.env.i agt.drv", "vif",input_if);
end
initial begin
uvm configdb#(virtual my_if)::set(uvm_root::get(),"uvm_test_top.env.i_ag t. drv", "vif", input_if); 
end

as the paraml and param2 joint the path, so we can do it like bellow:

uvm config db#(int)::set(this.env,"i_agt.drv","pre_num_max"，100);
uvm config db#(int)::get(this.parent, "drv","pre_num_max", pre_num_max);
uvm config db#(int)::get(null,"uvm_test_top.env.i_agt.drv","pre_num_max", p re_num_max) ;

3.5.3 omit the get calling

if use “uvm filedint’register, and calling the 'super.build_phase’int build phase, you can omit the get calling
uvm config_db#(int)::get(this,”",“pre_num”, pre_num);
why? the key point is the calling of the 'super.build_phase’in build_phase, when the driver calling the super.build_phase
the get calling will be execute automiclly
the pre-conditions is :
1.my driver must be registered by uvm_component_utils
2. the pre num must be registered by uvm_field_int
3. the set function’s third params must be the same as the get , like ‘pre_num’

3.5.4 muti leyel set/get

3.5.4 normal:
the higher the hierarchy the higher priority
3.5.4 abnormal
the hierarchy is same uvm root::get() which means the uvm top. so the time is the rules:
the least send, the higher priority<as the build_phase execute from top to bottom, so the my_case0’build_phase early than the my env’build phase>

3.5.5 same level set/get

set in base case, extends in sub cases

3.5.6 none line level set/get

line set:in uvm test top, env, i_agt use config_db set driver members
none line set:inothers component,use config_db set driver members, such as scoreboard
tine get:in my driver uses config_db get others components set values
none line get: in others component get the others components set values for my_driver

3.5.7 config db mechanism support wildcard character

// uvm_config_db(virtual myif)::set(null,"um test top.env.iagt.dry","vif",inputif);//uvm configdb, tree root:uvmtest_top.drv, drv same as the my_ens.sv create name
// uvm_config_db#(virtual my_if)::set(null, "uvm test top.env.i_agt.mon", "vif", input_if);
// uvm_config_db#(virtual my_if)::set(null,"uvm_test_top.env.o_agt.mon","vif", output_if);
// uvm_config_db#(virtual my if)::set(null,"uvm test top.env.i agt*","vif",inputif)://uvmconfigdb. tree rpot:uvmtest_top.drv, drv same as the my_ens.sv create name
// uvm_config_db#(virtual my_if)::set(null,"uvm_test_top.env.o_agt.mon","vif",output_if);
uvm_config_db#(virtual myif)::set(null,"*i agt*","vif",inputif);//uvm_config_db, tree root:uvm_test_top.drv, drv same as the my_ens.sv create name
uvm_config_db#(virtual my_if)::set(null,"*o_agt*","vif",output_if); end

3.5.8 check config usage

3.5.9 set config a get config

3.5.10 config db debug

check config_usage
print config(1)//1: recursive ;0: only display current component info
command: +UVM CONFIG DB TRACE
the method will not display info about param2, the debugmethod will showin10.6.3, it will check set function canbe reach, if not, will show UVM ERROR

4 TLM1.0

4.1 UVM TLM1.0

1. component conmucation :

public variable
global variable
config mechanism
TLM

2. TLM

get
put
transport<request/response>

data control flow:

PORT:request
ExPORT:target

priority:
PORT > EXPORT > IMP

4.2 port connect

4.2.1 A PORT connect B EXPORT

bad when connect

4.2.2 A PORT connect B EXPORT, B EXPORT COnneCt B IMP

good connect, B component must impl put function

4.2.3 A port connect B imp

i> B component must impl put function
NOTE:A PORTput->B_EXPORT put->B_IMP put ->B component put: data tansport flow

4.2.4 A export connect B imp

4.2.5 port connect port

C PORT connect A PORT connect B IMP

4.2.6 export connect export

A PORT connect c EXPORT connect B EXPORT connect B IMP

4.2.7 blocking get

get feature is like put

4.2.8 blocking transport

duplex communication
the releationship of the blockingtransport_port/export/imp is like blocking_put

4.2.9 noblocking

4.3 UVM communication type

4.3.1 UVM analysis port/export

  analysis port and IMp:one for more which like broadcast
  put/get port and IMP: one for one <except when connect set one for more>

  put/get can use blocking and noblocking
  analysis port/export like broadcast, so not have the means of blocking/noblocking

  analysis port can connect more than one IMP but the type must bu uvm_analysis_imp

  put: put try_put can_put; get: get try_get can_get; analysis port/export: write

4.3.2 one component more than one IMP

1.2-13 o_agt’monitor communicate with scoreboard: third methods connect
2.marco :uvm analysis impdecl -> one component more imp

4.3.3 FIFO

uvm_tlm_analysis_fifo : has analysis export & write function
uvm_tlm _fifo: do not have analysis export
get:send a transaction, Fifo transaction count minus l
peek:send a copy of transaction, fifo transaton count keep same
FIFO debug:

used function: how many transaction FIFO cache has
is empty: empty or not
is full
size : return the upper limit
flush : flush all data, use reset
FIFO is a uvm component

function new(string name, uvm_component parent= null, int size=1)
// default cache sizeis 1, if you want the size is infinite size, set the size = 0;

4.3.4 FIFO Or IMP

FIFO:

hide the uvM’s IMP;
useful when one component has multi IMp
complex connection in the env, but it is more useful when use port array
eg:as the ref model has 16 port will communication with scoreboard

5 running test bench uvm

5.1 Phase

5.1.1 task phase function phase

whether consume time<$time>

function phase: build_phase, connect_phase, which not spend time
task phase : run phase
all the phase will be executed from up to down(9 phase/8 function phase/1 taskphase/12 sub task phase<reset/configure/main/shutdown>

build_phase 
connect_phase
end_of_elaboration_phase 
start_of_simulation_phase
                                                                          > pre_reset phase
                                                                          >reset_phase
                                                                          >post_reset_phase
                                                                          >pre_configure_phase>
                                                                          >configure_phase
run_phase<only one task phase>	                                          >post_configure_phase	
<concurrence runing which sub phase>	                                  >pre_main_phase	
                                                                          >main phase
                                                                          >post_main_phase
                                                                          >pre_shutdown_phase
                                                                          >shutdown_phase
                                                                          >pre shutdown phase
                                                                          >shutdown_phase
                                                                          >post_shutdown_phase
extract_phase 
check_phase
report_phase 
final_phase

fork
  begin
    run_phase(); 
  end 
  begin
    pre_reset_phase(); 
    reset_phase();
    post_reset_phase(); 
    pre_configure_phase(); 
    configure_phase();
    post_configure_phase(); 
    pre-main_phase(); 
    main_phase();
    post_main_phase(); 
    pre_shutdown_phase(); 
    shutdown_phase();
    post_shutdown_phase(); 
end join

5.1.2 sub task phase

5.1.3 sequence of the phase execute

9 phase from top to down
build phase from top to down
9 phase except build_phase down to top <connect_phase : driver/monitor connect_phase, then agent connect_phase>
brother releation and same level component the ececute sequence is dictinoary sequecne

run_phase/main_phase down to top
but sequence is different from the function_phase waiting the down phase(driver run_phase) executed finish and then ececuted up pahse(agent run phase)
it use the"fork… joinnone"start all the run_phase, so it is down to top start, executed concurrence;
for one component, the run_time(12 sub phase) is executed in order,butit is only in order execute, which is not the front phase executed finish
then execute next riaht now
instance a uvm_component : build phase
instance a uvm_object : any phase include build phase
sychronous:

run-time phase(multi-component)
run_phase & post_shutdown phase(single component)
run_phase & run_phase(multiponent)

5.1.4 UVM TREE Search

BSF
DSF

5.1.5 super.phase

for build phase, the component do the most important this is using configdb;:set params, if turn off the featur, in sub build phase can not use super.build phase
for other phase , uvm almost do nothing
for self deine component, do as needed

5.1.6 build phase has UVM_ERROR, stop simulator

5.1.7 phase goto

backward goto: goto the current run-time phase before run-time phase
forward goto: goto the current run-time phase after run-time phase and function phases

5.1.8 why must be phase

i do different things in different time

5.1.9 debug phase

<sim command> + UVM PHASE TRACE

5.1.10 phase overtime

uvm top.set timeout(‘time’, ‘override’) UVM DEFAULT TIMEOUT 9200s

<sim command> +UMVM_TIME0UT=<timeout>,<overridable>
<sim command> +UVM TIMEOUT="300nS, YES"

5.2 objection mechanism

in12 run-time phase :if user want to do something which spend some time, you must raise objection in this phase
run phase and run-time phase: if raise objection inrun-time phase, the run phase will be execute, but if the raise objection in run phase
and the run-time phases do notraise objection, the run-time phase will not be executed.

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