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1."WARNING:Route:455 - CLK Net:trn_clk_OBUF may have excessive skew&nBSP;

because 0 CLK pins and 1 NON_CLK pins failed to route using a CLK

template."

Solution

This message informs the user that some loads on the clock net are not

clock pins. Therefore, the clock template that is normally uSED to connect

clock pins will not be used to connect the loads. A different routing that

involves local routing will be used, potentially inducing some skew on the

clock net.

Opening your design in FPGA Editor will allow you to see what loads are

connected to the clock net, and the cause of the warnings.

The amount of skew on the net will be reported in the Place and Route

report.

If the loads on the net shown in FPGA Editor are in accord with your

design, the skew reported in the PAR report is not critical for the

design, and the timing constraint requirement on that net is met, then

this warning can be safely ignored.

实例原因：在代码中用到这样的语句时(aa’event and

aa=’1’)，aa不是时钟信号，最多只是时钟信号产生的一类周期信号，aa被作为了另一个

进程或模块的类似周期信号的作用。(我是在行场信号发生器中 出现的这样的问题，用产

生的行同步信号(行同步信号是由全局时钟信号驱动产生的)再去驱动产生场同步信号，产

生的场同步信号相对与输入的全局时钟，有一定 的倾斜)

2. "WARNING:Xst:647 - Input is never used."

or

"WARNING:Xst:648 - Output is never used."

Solution

This particular port has been declared in your HDL description, but does

not drive or is not driven by any internal logic.

Unused input ports will remain in the design, but they will be completely

unconnected. If the port is not intended to be used, this message can be

safely ignored. To avoid this message, reMOVe any loadless or sourceless

elements from your HDL description.

Output ports will remain in the final netlist and will be driven by a

本文标签： 解决方法常见语言ErrorISE

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