关于开发Spartan-7 xc7s6 FPGA综合编译时遇到的问题记录

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因为没有找到相关例程，板子也是不是官方的。因此在综合编译时遇到一些警告和错误，在这里记录一下，写的不是很正确，也希望有大佬能够指点一二。

1.设计中无约束

[Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.

[Constraints 18-5210] No constraints selected for write.

警告设计中无约束，实际上我是有约束文件的，在XILINX官方论坛上找到如下解释：

The message is found in Vivado versions 2018.2 through 2019.2.

This message has been removed from the 2020.1 version of Vivado as it was found to be confusing.

大概是由于版本bug，在2018.2和2019.2中可能会出现此警告，不会造成影响因此可以忽略该警告。

2.时钟约束时找不到正确时钟&非时钟信号出现在时钟约束选项栏

 在Timing Constraints Wizard的截图中可以看到，本应该被约束的系统时钟sys_clk变成了一个普通IO输入，或者同时出现时钟和普通io需要被约束情况。

没有时钟或找不到时钟是因为截图下方可以看到，sys_clk其实已经被约束过了，因为我使用了PLL的IP核，系统时钟进来直接接PLL后输出，系统默认对其进行了约束。

普通io出现在里面是因为我在一个模块里将其作为上升沿触发了（不好的写法）。"always@(posedge i_wr_n or negedge rst_n)",这样写的话，编译器会把它当作时钟处理，自然就会出现在时钟约束里等你约束了，这里建议如果是需要上升沿处理可以进行边沿检测，将上升沿转化为一个clock的高电平。或者按照提示添加约束。

不然运行run implementation会报错。

3.未约束配置电平

在生成比特流时出现如下警告：

[DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

Refer to the device configuration user guide for more information.

这是由于没有正确约束配置电平，如下演示：

根据提示对其约束 

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

这里需要注意约束电压要和原理图相对应。一般FPGA配置电压为1.8V，对应CFGBVS要约束为GND,如果CONFIG_VOLTAGE配置电压选择3.3，那么对应CFGBVS要约束为VCCO。

勘误：

        

        sparta_7系列fpga的配置由上表确定，截取自文档UG470第30页，这里配置为VCCO和3.3V，想了解原因和其他设置方式可以参考[DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties解决方法_虚怀若水的博客-CSDN博客

说点其他的：

在FPGA管脚原理图连接时可以参考官方文档，就算都是用户io，也尽量不要随意配置，尤其是多功能复用io，在文档中有注明

IMPORTANT: For Tandem PROM configuration, the configuration PERSIST property is required. In this case, a dual-purpose I/O that is used for stage 1 and stage 2 configuration cannot be repurposed as user I/O after stage 2 configuration is complete. 与君共勉！

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