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2023年12月25日发(作者：)

元器件交易网8995MMicrelKS8995MIntegrated 5-Port 10/100 Managed SwitchRev 1.12General DescriptionThe KS8995M is a highly integrated Layer-2 managed switchwith optimized BOM (Bill of Materials) cost for low port count,cost-sensitive 10/100Mbps switch systems. It also providesan extensive feature set such as tag/port-based VLAN, QoS(Quality of Service) priority, management, MIB counters, dualMII interfaces and CPU control/data interfaces to effectivelyaddress both current and emerging Fast Ethernet KS8995M contains five 10/100 transceivers with pat-ented mixed-signal low-power technology, five MAC (MediaAccess Control) units, a high-speed non-blocking switchfabric, a dedicated address look-up engine, and an on-chipframe buffer PHY units support 10BaseT and 100BaseTX. In addition,two of the PHY units support 100BaseFX (Ports 4 and 5).All support documentation can be found on Micrel’s web siteat es•Integrated switch with five MACs and five Fast Ethernettransceivers fully compliant to IEEE 802.3u standard•Shared memory based switch fabric with fully non-blocking configuration•1.4Gbps high-performance memory bandwidth•10BaseT, 100BaseTX and 100BaseFX modes (FX inPorts 4 and 5)•Dual MII configuration: MII-Switch (MAC or PHY modeMII) and MII-P5 (PHY mode MII)•IEEE 802.1q tag-based VLAN (16 VLANs, full-rangeVID) for DMZ port, WAN/LAN separation or inter-VLANswitch links•VLAN ID tag/untag options, per-port basis•Programmable rate limiting 0Mbps to 100Mbps, ingressand egress port, rate options for high and low priority,per-port-basis•Flow control or drop packet rate limiting (ingress port)•Integrated MIB counters for fully compliant statisticsgathering, 34 MIB counters per portFunctional DiagramAutoMDI/MDIXAutoMDI/MDIXAutoMDI/MDIXAutoMDI/MDIXAutoMDI/MDIXMII-P5MDC, MDI/OMII-SW or SNIControl Reg I/FLED0[5:1]LED1[5:1]LED2[5:1]10/100T/Tx 110/100T/Tx 210/100T/Tx 310/100T/Tx/Fx 410/100T/Tx/Fx 510/100MAC 110/100MAC 210/100MAC 310/100MAC 410/100MAC 5SNISPIFIFO, Flow Control, VLAN Tagging, Priority1K look-upEngineQueueMgmntBufferMgmntFrameBuffersMIBCountersEEPROMI/FLED I/FControlRegistersKS8995MMicrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • ember 20031M9999-120403

元器件交易网8995MFeatures

(continued)•Enable/Disable option for huge frame size up to 1916bytes per frame•IGMP v1/v2 snooping for multicast packet filtering•Special tagging mode to send CPU info on ingresspacket’s port value•SPI slave (complete) and MDIO (MII PHY only) serialmanagement interface for control of register configura-tion•MAC-id based security lock option•Control registers configurable on-the-fly (port-priority,802.1p/d/q, AN...)•CPU read access to MAC forwarding table entries•802.1d Spanning Tree Protocol•Port mirroring/monitoring/sniffing:ingress and/or egresstraffic to any port or MII•Broadcast storm protection with percent control–globaland per-port basis•Optimization for fiber-to-copper media conversion•Full-chip hardware power-down support (registerconfiguration not saved)•Per-port based software power-save on PHY (idle linkdetection, register configuration preserved)•QoS/CoS packets prioritization supports: per port,802.1p and DiffServ based•802.1p/q tag insertion or removal on a per port basis(egress)•MDC and MDI/O interface support to access the MIIPHY control registers (not all control registers)•MII local loopback support•On-chip 64Kbyte memory for frame buffering (notshared with 1K unicast address table)•Wire-speed reception and transmission•Integrated look-up engine with dedicated 1K MACaddresses•Full duplex IEEE 802.3x and half-duplex back pressureflow control•Comprehensive LED support•7-wire SNI support for legacy MAC interface•Automatic MDI/MDI-X crossover for plug-and-play•Disable Automatic MDI/MDI-X option•Low power:Core:1.8VI/O:2.5V or 3.3V•0.18µm CMOS technology•Commercial temperature range:0°C to +70°C•Industrial temperature range:–40°C to +85°C•Available in 128-pin PQFP packageMicrelApplications•••••••••Broadband gateway/firewall/VPNIntegrated DSL or cable modem multi-port routerWireless LAN access point plus gatewayHome networking expansionStandalone 10/100 switchHotel/campus/MxU gatewayEnterprise VoIP gateway/phoneFTTx customer premise equipmentManaged media converterOrdering InformationPart NumberKS8995MKSZ8995MKS8995MITemperature Range0°C to +70°C0°C to +70°C–40°C to +85°CPackage128-Pin PQFP128-Pin PQFP Lead Free128-Pin PQFPM9999-1204032December 2003

元器件交易网8995MRevision HistoryRevision1.001.011.021.031.04Date11/05/0111/09/0112/03/0112/12/0112/13/01Summary of ChangesCreatedPinout Mux1/2, DVCC-IO 2.5/3.3V, feature list, register spec 11-09MicrelEditorial changes, added new register and MIB descriptions. Added paragraph describing TOS ed functional descriptions. orate changes per engineering feedback as well as updating functional descriptions and addingnew timing d Rev. and For. Modes to PHY and MAC modes respectively. Added MIIM clarification in “MIIManagement Interface” section. Reformatted section sequence. Added hex register addresses. Addedadvertisement ability ed switch forwarding flow new KS8995M block diagram, editorial changes, register descriptions changes and cross-references from functional descriptions to register and strap in d FXSD pins to inputs, added new descriptions to “Configuration Interfaces” pin ial changes in “Dynamic MAC Address table and “MIB Counters.” Updated figure 2 d table 2 for MAC mode connections. Separate static MAC bit assignments for read and read and write examples to MAC tables and MIB counters. Changed Table 3 KS8995M signals to“S” suffix. Changed aging description in Register 2, bit 0. Changed “Port Registers” section and listed allport register addresses. Changed port control 11 description for bits [7:5]. Changed MIB d MII setting in “Pin Descriptions.” Changed pu/pd descriptions for SMRXD2. “Register 18,”changed pu/pd description for forced flow control. “Illegal Frames. ” Edited large packet sizes back in.“Elecrical Characteristics,” Added in typical supply current numbers for 100 BaseTX and 10 BaseTXoperation. “Register 18,” Added in note for illegal half-duplex, force flow control. “Pin Description,” Addedextra X1 clock input description. “Elecrical Characteristics,” Updated to chip only current SPI Timing. Feature Highlights.“Pin Description,” changed SMRXC and SMTXC to I/O. Input in MAC mode, output in PHY mode MII.“Elecrical Characteristics,” modified current consumption to chip only numbers. “Half-Duplex BackPressure,” added description for no dropped packets in half-duplex mode. Added recommendedoperating conditions. Added Idle mode current consumption in “Elecrical Characteristics,” added“Selection of Isolation Transformers,” Added 3.01kΩ resistor instructions for ISET “Pin Description”section. Changed Polarity of transmit pairs in “Pin Description.” Changed description for Register 2, bit 1,in “Register Description” section. Added “Reset Timing” section.“Register 3” changed 802.1x to 802.3x. “Register 6,” changed default column to disable flow control forpull-down, and enable flow control for pull-up. “Register 29” and “Register 0” indicate loop back is at thePHY. Added description to register 4 bit 2 to indicate that STPID packets from CPU to normal ports arenot allowed as 1522 byte tag packets. Fixed dynamic MAC address example errors in “Dynamic MACAddress Table.” Changed definition of forced MDI, MDIX in section “Register 29,” “Register 30” and“Register 0.” Added “Part Ordering Information.” Added Ambient operating temperature for KS8995MIChanged pin 120 description to NC. Changed SPIQ pin description to Otri. Changed logo. Changedcontact information.1.051.061.071.0812/18/0112/20/011/22/013/1/021.095/17/021.107/29/021.1112/17/021.123/10/03December 20033M9999-120403

元器件交易网8995MTable of ContentsMicrelSystem 7Pin Description (by Number)......................................................................................................................................9Pin Description (by Name)........................................................................................................................................22Functional Overview:Physical 22PLL 22Scrambler/De-scrambler (100BaseTX only)........................................................................................................22100BaseFX 22100BaseFX Far 23MDI/MDI-X 23Functional Overview:24Inter-Packet Gap (IPG).................................................................................................................................26Half-Duplex 26Broadcast .26MII 26SNI .28Spanning 28Special 30Port 31Rate 33I2C Master Serial 35SPI Slave Serial 35MII Management Interface (MIIM).......................................................................................................................38M9999-1204034December 2003

元器件交易网Register 0 (0x00): .Register 1 (0x01): Chip ID1/Register 2 (0x02): Global Register 3 (0x03): Global Register 4 (0x04): Global Register 5 (0x05): Global Register 6 (0x06): Global Register 7 (0x07): Global Register 8 (0x08): Global Register 9 (0x09): Global Register 10 (0x0A): Global .Register 11 (0x0B): Global .Register 16 (0x10):Port 1 .Register 17 (0x11):Port 1 .Register 18 (0x12):Port 1 .Register 19 (0x13):Port 1 .Register 20 (0x14):Port 1 .Register 21 (0x15):Port 1 .Register 22 (0x16):Port 1 .Register 23 (0x17):Port 1 .Register 24 (0x18):Port 1 .Register 25 (0x19):Port 1 .Register 26 (0x1A):Port 1 Register 27 (0x1B):Port 1 Register 28 (0x1C):Port 1 Register 29 (0x1D):Port 1 Register 30 (0x1E):Port 1 Register 31 (0x1F):Port 1 Advanced .Register 96 (0x60):TOS Priority Control Register 97 (0x61):TOS Priority Control Register 98 (0x62):TOS Priority Control Register 99 (0x63):TOS Priority Control Register 100 (0x64):TOS Priority Control Register 101 (0x65):TOS Priority Control Register 102 (0x66):TOS Priority Control Register 103 (0x67):TOS Priority Control Register 104 (0x68):MAC Address Register 105 (0x69):MAC Address Register 106 (0x6A):MAC Address Register 107 (0x6B):MAC Address Register 108 (0x6C):MAC Address Register 109 (0X6D):MAC Address Register 110 (0x6E):Indirect Access Register 111 (0x6F):Indirect Access December 20035Micrel3939393943434343444444454646464646474747474849495M9999-120403

元器件交易网8995MMicrelRegister 112 (0x70):Indirect Data .51Register 113 (0x71):Indirect Data .51Register 114 (0x72):Indirect Data .51Register 115 (0x73):Indirect Data .51Register 116 (0x74):Indirect Data .51Register 117 (0x75):Indirect Data .51Register 118 (0x76):Indirect Data .51Register 119 (0x77):Indirect Data .51Register 120 (0x78):Indirect Data .51Register 121 (0x79):Digital Testing 51Register 122 (0x7A):Digital Testing .51Register 123 (0x7B):Digital Testing 51Register 124 (0x7C):Digital Testing 51Register 125 (0x7D):Analog Testing 51Register 126 (0x7E):Analog Testing 52Register 127 (0x7F):Analog 52Static 55Dynamic 60Register 0: .60Register 1: 61Register 2: 61Register 3: 61Register 4: 61Register 5: Link 62Absolute .65Selection of 72Qualified 73M9999-1204036December 2003

元器件交易网8995MSystem Level Applications10/100MAC 1Switch

ControllerOn-Chip

Frame

BuffersMicrel10/100PHY 110/100PHY 210/100PHY 310/100PHY 410/100PHY 51-portWAN I/F4-portLAN10/100MAC 210/100MAC 310/100MAC 410/100MAC 5SPI/GPIOSPIEthernetMACCPUEthernetMACMII-SWMII-P5External WAN port PHY not neededFigure and Gateway10/100MAC 1Switch

ControllerOn-Chip

Frame

Buffers10/100PHY 110/100PHY 210/100PHY 310/100PHY 410/100PHY 54-portLAN10/100MAC 210/100MAC 310/100MAC 410/100MAC 5WAN PHY & AFE(xDSL, CM...)CPUSPI/GPIOSPIMII-SWMII-P5EthernetMACFigure ated Broadband RouterDecember 20037M9999-120403

元器件交易网8995MMicrel10/100MAC 1Switch

ControllerOn-Chip

Frame

Buffers10/100PHY 110/100PHY 210/100PHY 310/100PHY 410/100PHY 55-portLAN10/100MAC 210/100MAC 310/100MAC 410/100MAC 5Figure lone SwitchM9999-1204038December 2003

元器件交易网8995MPin Description (by Number)Pin Number8293031Pin NameTEST1GNDAVDDARRXP1RXM1GNDATXM1TXP1VDDATRXP2RXM2GNDATXM2TXP2VDDARGNDAISETVDDATRXP3RXM3GNDATXM3TXP3VDDATRXP4RXM4GNDATXM4TXP4GNDAVDDARPIIGndOOPIIGndOOGndP44443333Type(1)NCGndPIIGndOOPIIGndOOPGnd22221111PortPin FunctionNC for normal operation. Factory test ground1.8V analog VDDPhysical receive signal + (differential)Physical receive signal - (differential)Analog groundPhysical transmit signal - (differential)Physical transmit signal + (differential)2.5V analog VDDPhysical receive signal + (differential)Physical receive signal - (differential)Analog groundPhysical transmit signal - (differential)Physical transmit signal + (differential)1.8V analog VDDAnalog groundSet physical transmit output current. Pull-down with a 3.01kΩ 1%resistor.2.5V analog VDDPhysical receive signal + (differential)Physical receive signal - (differential)Analog groundPhysical transmit signal - (differential)Physical transmit signal + (differential)2.5V analog VDDPhysical receive signal + (differential)Physical receive signal - (differential)Analog groundPhysical transmit signal - (differential)Physical transmit signal + (differential)Analog ground1.8V analog VDDMicrelNote:1.P = Power supplyI = InputO = OutputI/O = Bi-directionalGnd = GroundIpu = Input w/ internal pull-upIpd = Input w/ internal pull-downIpd/O = Input w/ internal pull-down during reset, output pin otherwiseIpu/O = Input w/ internal pull-up during reset, output pin otherwisePU = Strap pin pull-upPD = Strap pin pull-downOtri = Output tristatedNC = No ConnectDecember 20039M9999-120403

元器件交易网8995MPin Number323334353637383946Pin NameRXP5RXM5GNDATXM5TXP5VDDATFXSD5FXSD4GNDAVDDARGNDAVDDARGNDAMUX1MUX2Type(1)IIGndOOPIIGndPGndPGndNCNC5455Port55Pin FunctionPhysical receive signal + (differential)Physical receive signal - (differential)Analog groundPhysical transmit signal - (differential)Physical transmit signal + (differential)2.5V analog VDDFiber signal detect/factory test pinFiber signal detect/factory test pinAnalog ground1.8V analog VDDAnalog ground1.8V analog VDDAnalog groundMUX1 and MUX2 should be left unconnected for normal are factory test rmal OperationRemote Analog Loopback Mode for Testing onlyReservedPower Save Mode for Testing only474849565758Note:1.P = Power supplyI = InputO = OutputI/O = Bi-directionalGnd = GroundIpu = Input w/ internal pull-upIpd = Input w/ internal pull-downIpd/O = Input w/ internal pull-down during reset, output pin otherwiseIpu/O = Input w/ internal pull-up during reset, output pin otherwisePU = Strap pin pull-upPD = Strap pin pull-downOtri = Output tristatedNC = No ConnectMicrelMux1NC011Mux2NC101PWRDN_NRESERVEGNDDVDDCPMTXENPMTXD3PMTXD2PMTXD1PMTXD0PMTXERPMTXCGNDDIpuNCGndPIpdIpdIpdIpdIpdIpdOGnd5555555Full-chip power down. Active ed pin. No l ground1.8V digital core VDDPHY[5] MII transmit enablePHY[5] MII transmit bit 3PHY[5] MII transmit bit 2PHY[5] MII transmit bit 1PHY[5] MII transmit bit 0PHY[5] MII transmit errorPHY[5] MII transmit clock. PHY mode l groundM9999-12040310December 2003

元器件交易网8995MPin Number596Pin NameVDDIOPMRXCPMRXDVPMRXD3PMRXD2PMRXD1PMRXD0Type(1)POIpd/OIpd/OIpd/OIpd/OIpd/O555555PortPin Function3.3/2.5V digital VDD for digital I/O circuitryPHY[5] MII receive clock. PHY mode MIIPHY[5] MII receive data validPHY[5] MII receive bit 3. Strap option:PD (default) = enable flowcontrol; PU = disable flow [5] MII receive bit 2. Strap option:PD (default) = disable backpressure; PU = enable back PHY[5] MII receive bit 1. Strap option:PD (default) = drop excessivecollision packets; PU = does not drop excessive collision [5] MII receive bit 0. Strap option: PD (default) = disableaggressive back-off algorithm in half-duplex mode; PU = enable forperformance [5] MII receive error. Strap option:PD (default) = 1522/1518 bytes;PU = packet size up to 1536 [5] MII carrier sense/Force duplex mode. See

“Register 76”

forport 4 only. PD (default) = Force half-duplex if auto-negotiation isdisabled or fails. PU = Force full-duplex if auto-negotiation is disabledor [5] MII collision detect/ Force flow control. See

“Register 66”

forport 4 only. PD (default) = No force flow control. PU = Force MII transmit enableSwitch MII transmit bit 3Switch MII transmit bit 2Switch MII transmit bit 1Switch MII transmit bit 0Switch MII transmit errorSwitch MII transmit clock. Input in MAC mode, output in PHY mode l ground3.3/2.5V digital VDD for digital I/O circuitrySwitch MII receive clock. Input in MAC mode, output in PHY mode MII receive data validSwitch MII receive bit 3. Strap option: PD (default) = Disable Switch MIIfull-duplex flow control; PU = Enable Switch MII full-duplex flow MII receive bit 2. Strap option: PD (default) = Switch MII in full-duplex mode; PU = Switch MII in half-duplex mode.6667PMRXERPCRSIpd/OIpd/O5568PCOLIpd/O569767778798081Note:1.P = Power supplyI = InputO = OutputI/O = Bi-directionalGnd = GroundSMTXENSMTXD3SMTXD2SMTXD1SMTXD0SMTXERSMTXCGNDDVDDIOSMRXCSMRXDVSMRXD3SMRXD2IpdIpdIpdIpdIpdIpdI/OGndPI/OIpd/OIpd/OIpd/OIpu = Input w/ internal pull-upIpd = Input w/ internal pull-downIpd/O = Input w/ internal pull-down during reset, output pin otherwiseIpu/O = Input w/ internal pull-up during reset, output pin otherwisePU = Strap pin pull-upPD = Strap pin pull-downOtri = Output tristatedNC = No ConnectDecember 200311M9999-120403

元器件交易网8995MPin Number8283Pin NameSMRXD1SMRXD0Type(1)Ipd/OIpd/OPortPin FunctionSwitch MII receive bit 1. Strap option: PD (default) = Switch MII in100Mbps mode; PU = Switch MII in 10Mbps MII receive bit 0; Strap option: LED ModePD (default) = Mode 0; PU = Mode 1. See

“Register 11.”Mode 0LEDX_2LEDX_1LEDX_0848586SCOLSCRSSCONF1Ipd/OIpd/OIpdSwitch MII collision detectSwitch MII carrier senseDual MII configuration pinPin# (91, 86, 87):1788899697SCONF0GNDDVDDCLED5-2LED5-1LED5-0LED4-2LED4-1LED4-0LED3-2LED3-1IpdGndPIpu/OIpu/OIpu/OIpu/OIpu/OIpu/OIpu/OIpu/O55544433Switch MIIDisable, OtriPHY Mode MIIMAC Mode MIIPHY Mode SNIDisablePHY Mode MIIMAC Mode MIIPHY Mode SNIPHY [5] MIIDisable, OtriDisable, OtriDisable, OtriDisable, OtriDisablePHY Mode MIIPHY Mode MIIPHY Mode MIILnk/ActFulld/ColSpeedMicrelMode 1100Lnk/Act10Lnk/ActFulldDual MII configuration pinDigital ground1.8V digital core VDDLED indicator 2. Strap option: Aging setup. See

“Aging” sectionPU (default) = Aging Enable; PD = Aging indicator 1. Strap option: PU (default): enable PHY MII I/FPD:tristate all PHY MII output. See

“pin# 86 SCONF1.”LED indicator 0LED indicator 2LED indicator 1LED indicator 0LED indicator 2LED indicator 1Note:1.P = Power supplyI = InputO = OutputI/O = Bi-directionalGnd = GroundIpu = Input w/ internal pull-upIpd = Input w/ internal pull-downIpd/O = Input w/ internal pull-down during reset, output pin otherwiseIpu/O = Input w/ internal pull-up during reset, output pin otherwisePU = Strap pin pull-upPD = Strap pin pull-downOtri = Output tristatedNC = No ConnectM9999-12040312December 2003

元器件交易网8995MPin Number9899112Pin NameLED3-0GNDDVDDIOLED2-2LED2-1LED2-0LED1-2LED1-1LED1-0MDCMDIOSPIQSPIC/SCLSPID/SDASPIS_NType(1)Ipu/OGndPIpu/OIpu/OIpu/OIpu/OIpu/OIpu/OIpuI/OOtriI/OI/OIpu222111AllAllAllAllAllAllPort3Pin FunctionLED indicator 0Digital ground3.3/2.5V digital VDD for digital I/OLED indicator 2LED indicator 1LED indicator 0LED indicator 2LED indicator 1LED indicator 0Switch or PHY[5] MII management data clockSwitch or PHY[5] MII management data I/es internal pull down to define pin state when not (1) SPI serial data output in SPI slave mode; (2) Not used in I2C mastermode. See

“pin# 113.”(1) Input clock up to 5MHz in SPI slave mode; (2) Output clock at81KHz in I2C master mode. See

“pin# 113.”(1) Serial data input in SPI slave mode; (2) Serial data input/output inI2C master mode See

“pin# 113.”Active low. (1) SPI data transfer start in SPI slave mode. When SPIS_Nis high, the KS8995M is deselected and SPIQ is held in high impedancestate, a high-to-low transition to initiate the SPI data transfer; (2) Notused in I2C master bus configuration pinIf EEPROM is not present, the KS8995M will start itself with chipdefault (00)...Pin [1:0]=00PS[1:0]=01PS[1:0]=10PS[1:0]=11Serial Bus ConfigurationI2C Master Mode for EEPROMReservedSPI Slave Mode for CPU InterfaceFactory Test Mode (BIST)113PS1Ipd7118Note:1.P = Power supplyI = InputO = OutputI/O = Bi-directionalGnd = GroundPS0RST_NGNDDVDDCTESTENIpdIpuGndPIpdSerial bus configuration pin. See

“pin# 113.”Reset the KS8995M. Active l ground1.8V digital core VDDNC for normal operation. Factory test = Input w/ internal pull-upIpd = Input w/ internal pull-downIpd/O = Input w/ internal pull-down during reset, output pin otherwiseIpu/O = Input w/ internal pull-up during reset, output pin otherwisePU = Strap pin pull-upPD = Strap pin pull-downOtri = Output tristatedNC = No ConnectDecember 200313M9999-120403

元器件交易网8995MPin Number6127128Note:1.P = Power supplyI = InputO = OutputI/O = Bi-directionalGnd = GroundIpu = Input w/ internal pull-upIpd = Input w/ internal pull-downIpd/O = Input w/ internal pull-down during reset, output pin otherwiseIpu/O = Input w/ internal pull-up during reset, output pin otherwisePU = Strap pin pull-upPD = Strap pin pull-downOtri = Output tristatedNC = No ConnectMicrelPortPin FunctionNC for normal operation. Factory test Connect25MHz crystal clock connection/or 3.3V tolerant oscillator ator should be ±100ppm.25MHz crystal clock connection1.8V analog VDD for PLLAnalog ground1.8V analog VDDAnalog groundAnalog groundNC for normal operation. Factory test NameSCANENNCX1X2VDDAPGNDAVDDARGNDAGNDATEST2Type(1)IpdNCIOPGndPGndGndNCM9999-12040314December 2003

元器件交易网8995MPin Description (by Name)Pin Number3938710210198Pin NameFXSD4FXSD5GNDAGNDAGNDAGNDAGNDAGNDAGNDAGNDAGNDAGNDAGNDAGNDANCGNDAGNDAGNDDGNDDGNDDGNDDGNDDGNDDISETLED1-0LED1-1LED1-2LED2-0LED2-1LED2-2LED3-0Ipu/OIpu/OIpu/OIpu/OIpu/OIpu/OIpu/O1112223Type(1)IIGndGndGndGndGndGndGndGndGndGndGndGndNCGndGndGndGndGndGndGndGndPort45Pin FunctionFiber signal detect/factory test signal detect/factory test groundAnalog groundAnalog groundAnalog groundAnalog groundAnalog groundAnalog groundAnalog groundAnalog groundAnalog groundAnalog groundAnalog groundNo connectAnalog groundAnalog groundDigital groundDigital groundDigital groundDigital groundDigital groundDigital groundSet physical transmit output current. Pull-down with a 3.01kΩ 1% indicator 0LED indicator 1LED indicator 2LED indicator 0LED indicator 1LED indicator 2LED indicator 0MicrelNote:1.P = Power supplyI = InputO = OutputI/O = Bi-directionalGnd = GroundIpu = Input w/ internal pull-upIpd = Input w/ internal pull-downIpd/O = Input w/ internal pull-down during reset, output pin otherwiseIpu/O = Input w/ internal pull-up during reset, output pin otherwisePU = Strap pin pull-upPD = Strap pin pull-downOtri = Output tristatedNC = No ConnectDecember 200315M9999-120403

元器件交易网8995MPin Number979695949392919Pin NameLED3-1LED3-2LED4-0LED4-1LED4-2LED5-0LED5-1LED5-2MDCMDIOTEST1MUX1MUX2Type(1)Ipu/OIpu/OIpu/OIpu/OIpu/OIpu/OIpu/OIpu/OIpuI/ONCNCNCPort33444555AllAllPin FunctionLED indicator 1LED indicator 2LED indicator 0LED indicator 1LED indicator 2LED indicator 0LED indicator 1. Strap option:PU (default): enable PHY MII I/:tristate all PHY MII output. See

“pin# 86 SCONF1.”LED indicator 2. Strap option: Aging setup. See

“Aging” section.(default) = Aging Enable;PD = Aging disableSwitch or PHY[5] MII management data or PHY[5] MII management data I/ for normal operation. Factory test 1 and MUX2 should be left unconnected for normal are factory test rmal OperationRemote Analog Loopback Mode for Testing onlyReservedPower Save Mode for Testing only68PCOLIpd/O5Mux1NC011MicrelMux2NC101PHY[5] MII collision detect/Force flow control. See

“Register 18.”For port 4 only. PD (default) = No force flow control. PU = Force [5] MII carrier sense/Force duplex mode See

“Register 28.”For port 4 only. PD (default) = Force half-duplex if auto-negotiation isdisabled or fails. PU = Force full-duplex if auto-negotiation is disabledor [5] MII receive clock. PHY mode [5] MII receive bit 0. Strap option: PD (default) = disableaggressive back-off algorithm in half-duplex mode; PU = enable forperformance [5] MII receive bit 1. Strap option: PD (default) = drop excessivecollision packets; PU = does not drop excessive collision [5] MII receive bit 2. Strap option: PD (default) = disable backpressure; PU = enable back [5] MII receive bit 3. Strap option: PD (default) = enable flowcontrol; PU = disable flow control.67PCRSIpd/O56065PMRXCPMRXD0OIpd/O55646362PMRXD1PMRXD2PMRXD3Ipd/OIpd/OIpd/O555Note:1.P = Power supplyI = InputO = OutputI/O = Bi-directionalGnd = GroundIpu = Input w/ internal pull-upIpd = Input w/ internal pull-downIpd/O = Input w/ internal pull-down during reset, output pin otherwiseIpu/O = Input w/ internal pull-up during reset, output pin otherwisePU = Strap pin pull-upPD = Strap pin pull-downOtri = Output tristatedNC = No ConnectM9999-12040316December 2003

元器件交易网8995MPin Number6525156114113Pin NamePMRXDVPMRXERPMTXCPMTXD0PMTXD1PMTXD2PMTXD3PMTXENPMTXERPS0PS1Type(1)Ipd/OIpd/OOIpdIpdIpdIpdIpdIpdIpdIpdPort555555555Pin FunctionPHY[5] MII receive data PHY[5] MII receive error. Strap option: PD (default) = 1522/1518 bytes;PU = packet size up to 1536 [5] MII transmit clock. PHY mode MIIPHY[5] MII transmit bit 0PHY[5] MII transmit bit 1PHY[5] MII transmit bit 2PHY[5] MII transmit bit 3PHY[5] MII transmit enablePHY[5] MII transmit errorSerial bus configuration pin. See

“pin# 113.”Serial bus configuration pinIf EEPROM is not present, the KS8995M will start itself with chipdefault (00)...Pin [1:0]=00PS[1:0]=01PS[1:0]=10PS[1:0]=11Serial Bus ConfigurationI2C Master Mode for EEPROMReservedSPI Slave Mode for CPU InterfaceFactory Test Mode (BIST)4748984PWRDN_NRESERVERST_NRXM1RXM2RXM3RXM4RXM5RXP1RXP2RXP3RXP4RXP5SCANENSCOLIpuNCIpuIIIIIIIIIIIpdIpd/O1234512345Full-chip power down. Active ed pin. No the KS8995M. Active al receive signal - (differential)Physical receive signal - (differential)Physical receive signal - (differential)Physical receive signal - (differential)Physical receive signal - (differential)Physical receive signal + (differential)Physical receive signal + (differential)Physical receive signal + (differential)Physical receive signal + (differential)Physical receive signal + (differential)NC for normal operation. Factory test MII collision :1.P = Power supplyI = InputO = OutputI/O = Bi-directionalGnd = GroundIpu = Input w/ internal pull-upIpd = Input w/ internal pull-downIpd/O = Input w/ internal pull-down during reset, output pin otherwiseIpu/O = Input w/ internal pull-up during reset, output pin otherwisePU = Strap pin pull-upPD = Strap pin pull-downOtri = Output tristatedNC = No ConnectDecember 200317M9999-120403

元器件交易网8995MPin Number8786Pin NameSCONF0SCONF1Type(1)IpdIpdPortPin FunctionDual MII configuration pinDual MII configuration pinPin# (91, 86, 87):157883SCRSSMRXCSMRXD0Ipd/OI/OIpd/OSwitch MII carrier senseSwitch MIIDisable, OtriPHY Mode MIIMAC Mode MIIPHY Mode SNIDisablePHY Mode MIIMAC Mode MIIPHY Mode SNIPHY [5] MIIDisable, OtriDisable, OtriDisable, OtriDisable, OtriDisablePHY Mode MIIPHY Mode MIIPHY Mode MIIMicrelSwitch MII receive clock. Input in MAC mode, output in PHY mode MII receive bit 0; Strap option: LED ModePD (default) = Mode 0; PU = Mode 1. See

“Register 11.”Mode 0LEDX_2LEDX_1LEDX_0Lnk/ActFulld/ColSpeedMode 1100Lnk/Act10Lnk/ActFulld8281806974SMRXD1SMRXD2SMRXD3SMRXDVSMTXCSMTXD0SMTXD1SMTXD2SMTXD3SMTXENSMTXERIpd/OIpd/OIpd/OIpd/OI/OIpdIpdIpdIpdIpdIpdSwitch MII receive bit 1. Strap option:PD (default) = Switch MII in100Mbps mode; PU = Switch MII in 10Mbps MII receive bit 2. Strap option:PD (default) = Switch MII infull-duplex mode; PU = Switch MII in half-duplex MII receive bit 3. Strap option:PD (default) = Disable SwitchMII full-duplex flow control; PU = Enable Switch MII full-duplex flow MII receive data validSwitch MII transmit clock. Input in MAC mode, output in PHY mode MII transmit bit 0Switch MII transmit bit 1Switch MII transmit bit 2Switch MII transmit bit 3Switch MII transmit enableSwitch MII transmit errorNote:1.P = Power supplyI = InputO = OutputI/O = Bi-directionalGnd = GroundIpu = Input w/ internal pull-upIpd = Input w/ internal pull-downIpd/O = Input w/ internal pull-down during reset, output pin otherwiseIpu/O = Input w/ internal pull-up during reset, output pin otherwisePU = Strap pin pull-upPD = Strap pin pull-downOtri = Output tristatedNC = No ConnectM9999-12040318December 2003

元器件交易网8995MPin Number11Pin NameSPIC/SCLSPID/SDASPIQSPIS_NType(1)I/OI/OOtriIpuPortAllAllAllAllPin FunctionMicrel(1) Input clock up to 5MHz in SPI slave mode; (2) Output clock at 81KHzin I2C master mode. See

“pin# 113.”(1) Serial data input in SPI slave mode; (2) Serial data input/output inI2C master mode. See

“pin# 113.”(1) SPI serial data output in SPI slave mode; (2) Not used in I2C mastermode. See

“pin# 113.”Active low. (1) SPI data transfer start in SPI slave mode. When SPIS_Nis high, the KS8995M is deselected and SPIQ is held in high impedancestate, a high-to-low transition to initiate the SPI data transfer; (2) Notused in I2C master connect for normal operation. Factory test Connect for normal operation. Factory test pin.293674189243750TEST2TESTENTXP1TXP2TXP3TXP4TXP5TXM1TXM2TXM3TXM4TXM5VDDAPVDDARVDDARVDDARVDDARVDDARVDDARVDDATVDDATVDDATVDDATVDDCNCIpdOOOOOOOOOOPPPPPPPPPPPP1234512345Physical transmit signal + (differential)Physical transmit signal + (differential)Physical transmit signal + (differential)Physical transmit signal + (differential)Physical transmit signal + (differential)Physical transmit signal - (differential)Physical transmit signal - (differential)Physical transmit signal - (differential)Physical transmit signal - (differential)Physical transmit signal - (differential)1.8V analog VDD for PLL1.8V analog VDD1.8V analog VDD1.8V analog VDD1.8V analog VDD1.8V analog VDD1.8V analog VDD2.5V analog VDD2.5V analog VDD2.5V analog VDD2.5V analog VDD1.8V digital core VDDNote:1.P = Power supplyI = InputO = OutputI/O = Bi-directionalGnd = GroundIpu = Input w/ internal pull-upIpd = Input w/ internal pull-downIpd/O = Input w/ internal pull-down during reset, output pin otherwiseIpu/O = Input w/ internal pull-up during reset, output pin otherwisePU = Strap pin pull-upPD = Strap pin pull-downOtri = Output tristatedNC = No ConnectDecember 200319M9999-120403

元器件交易网8995MPin Number8921122Pin NameVDDCVDDCVDDIOVDDIOVDDIOX1X2Type(1)PPPPPIOPortPin Function1.8V digital core VDD1.8V digital core VDD3.3/2.5V digital VDD for digital I/O circuitry3.3/2.5V digital VDD for digital I/O circuitry3.3/2.5V digital VDD for digital I/O circuitry25MHz crystal clock connection/or 3.3V tolerant oscillator ator should be ±100ppm.25MHz crystal clock Note:1.P = Power supplyI = InputO = OutputI/O = Bi-directionalGnd = GroundIpu = Input w/ internal pull-upIpd = Input w/ internal pull-downIpd/O = Input w/ internal pull-down during reset, output pin otherwiseIpu/O = Input w/ internal pull-up during reset, output pin otherwisePU = Strap pin pull-upPD = Strap pin pull-downOtri = Output tristatedNC = No ConnectM9999-12040320December 2003

元器件交易网8995MDecember 2003LED2-0LED1-2LED1-1LED1-0MDCMDIOSPIQSPIC/SCLSPID/SDASPIS_NPS1PS0RST_NGNDDVDDCTESTENSCANENNCX1X2VDDAPGNDAVDDARGNDAGNDATEST21031Pin Configuration128-Pin PQFP (PQ)213965TEST1GNDAVDDARRXP1RXM1GNDATXM1TXP1VDDATRXP2RXM2GNDATXM2TXP2VDDARGNDAISETVDDATRXP3RXM3GNDATXM3TXP3VDDATRXP4RXM4GNDATXM4TXP4GNDAVDDARRXP5RXM5GNDATXM5TXP5VDDATFXSD5LED2-1LED2-2VDDIOGNDDLED3-0LED3-1LED3-2LED4-0LED4-1LED4-2LED5-0LED5-1LED5-2VDDCGNDDSCONF0SCONF1SCRSSCOLSMRXD0SMRXD1SMRXD2SMRXD3SMRXDVSMRXCVDDIOGNDDSMTXCSMTXERSMTXD0SMTXD1SMTXD2SMTXD3SMTEXNPCOLPCRSPMRXERPMRXD0PMRXD1PMRXD2PMRXD3PMRXDVPMRXCVDDIOGNDDPMTXCPMTXERPMTXD0PMTXD1PMTXD2PMTXD3PMTXENVDDCGNDDRESERVEPWRDN_NMUX2MUX1GNDAVDDARGNDAVDDARGNDAFXSD4M9999-120403Micrel

元器件交易网8995MIntroductionMicrelThe KS8995M contains five 10/100 physical layer transceivers and five MAC (Media Access Control) units with an integratedlayer 2 managed switch. The device runs in three modes. The first mode is as a five-port integrated switch. The second is asa five-port switch with the fifth port decoupled from the physical port. In this mode access to the fifth MAC is provided throughan MII (Media Independent Interface). This is useful for implementing an integrated broadband router. The third mode usesthe dual MII feature to recover the use of the fifth PHY. This allows the additional broadband gateway configuration, where thefifth PHY may be accessed through the MII-P5 KS8995M has the flexibility to reside in a managed or unmanaged design. In a managed design, a host processor hascomplete control of the KS8995M via the SPI bus, or partial control via the MDC/MDIO interface. An unmanaged design isachieved through I/O strapping or EEPROM programming at system reset the media side, the KS8995M supports IEEE 802.3 10BaseT, 100BaseTX on all ports, and 100BaseFX on ports 4 and KS8995M can be used as two separate media al signal transmission and reception are enhanced through the use of patented analog circuitry that makes the designmore efficient and allows for lower power consumption and smaller chip die major enhancements from the KS8995E to the KS8995M are support for host processor management, a dual MII interface,tag as well as port based VLAN, spanning tree protocol support, IGMP snooping support, port mirroring support and rate onal Overview:Physical Layer Transceiver100BaseTX TransmitThe 100BaseTX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion,MLT3 encoding and transmission. The circuit starts with a parallel-to-serial conversion, which converts the MII data from theMAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding followed by a serialized data is further converted from NRZ to NRZI format, and then transmitted in MLT3 current output. The outputcurrent is set by an external 1% 3.01kΩ resistor for the 1:1 transformer ratio. It has a typical rise/fall time of 4ns and complieswith the ANSI TP-PMD standard regarding amplitude balance, overshoot and timing jitter. The wave-shaped 10BaseT outputis also incorporated into the 100BaseTX transmitter.100BaseTX ReceiveThe 100BaseTX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and clockrecovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding and serial-to-parallel conversion. The receiving sidestarts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Since theamplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its characteristics tooptimize the performance. In this design, the variable equalizer will make an initial estimation based on comparisons ofincoming signal strength against some known cable characteristics, it then tunes itself for optimization. This is an ongoingprocess and can self-adjust against environmental changes such as temperature equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used tocompensate for the effect of baseline wander and improve the dynamic range. The differential data conversion circuit convertsthe MLT3 format back to NRZI. The slicing threshold is also clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used toconvert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by the 4B/5B y, the NRZ serial data is converted to the MII format and provided as the input data to the Clock SynthesizerThe KS8995M generates 125MHz, 42MHz, 25MHz and 10MHz clocks for system timing. Internal clocks are generated froman external 25MHz crystal or ler/De-scrambler (100BaseTX only)The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. Thedata is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). This can generate a 2047-bit non-repetitive sequence. The receiver will then de-scramble the incoming data stream with the same sequence at the transmitter.100BaseFX Operation100BaseFX operation is very similar to 100BaseTX operation except that the scrambler/de-scrambler and MLT3 encoder/decoder are bypassed on transmission and reception. In this mode the auto-negotiation feature is bypassed since there is nostandard that supports fiber auto-negotiation.100BaseFX Signal DetectionThe physical port runs in 100BaseFX mode if FXSDx >0.6V for ports 4 and 5 only. This signal is internally referenced to fiber module interface should be set by a voltage divider such that FXSDx ‘H’ is above this 1.25V reference, indicating signalM9999-12040322December 2003

元器件交易网8995MMicreldetect, and FXSDx ‘L’ is below the 1.25V reference to indicate no signal. When FXSDx is below 0.6V then 100BaseFX modeis disabled. Since there is no auto-negotiation for 100BaseFX mode, ports 4 and 5 must be forced to either full or that strap in options exist to set duplex mode for port 4, but not for port 5.100BaseFX Far End FaultFar end fault occurs when the signal detection is logically false from the receive fiber module. When this occurs, thetransmission side signals the other end of the link by sending 84 1s followed by a zero in the idle period between frames. Thefar end fault may be disabled through register settings.10BaseT TransmitThe output 10BaseT driver is incorporated into the 100BaseT driver to allow transmission with the same magnetics. They areinternally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude. The harmonic contents are at least27dB below the fundamental when driven by an all-ones Manchester-encoded signal.10BaseT ReceiveOn the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and aPLL perform the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. Asquelch circuit rejects signals with levels less than 400mV or with short pulse widths in order to prevent noises at the RXP orRXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signaland the KS8995M decodes a data frame. The receiver clock is maintained active during idle periods in between data ManagementThe KS8995M features a per port power down mode. To save power the user can power down ports that are not in use by settingport control registers or MII control registers. In addition, it also supports full chip power down mode. When activated, the entirechip will be shut /MDI-X Auto CrossoverThe KS8995M supports MDI/MDI-X auto crossover. This facilitates the use of either a straight connection CAT-5 cable or acrossover CAT-5 cable. The auto-sense function will detect remote transmit and receive pairs, and correctly assign the transmitand receive pairs from the Micrel device. This can be highly useful when end users are unaware of cable types and can alsosave on an additional uplink configuration connection. The auto crossover feature may be disabled through the port -NegotiationThe KS8995M conforms to the auto-negotiation protocol as described by the 802.3 committee. Auto-negotiation allows UTP(Unshielded Twisted Pair) link partners to select the best common mode of operation. In auto-negotiation the link partnersadvertise capabilities across the link to each other. If auto-negotiation is not supported or the link partner to the KS8995M isforced to bypass auto-negotiation, then the mode is set by observing the signal at the receiver. This is known as parallel modebecause while the transmitter is sending auto-negotiation advertisements, the receiver is listening for advertisements or a fixedsignal flow for the link set up is depicted in Figure Auto NegotiationForce Link SettingNoParallelOperationYesBypassAuto-Negotiationand Set Link ModeAttemptAuto-NegotiationListen for 100BaseTXIdlesListen for 10BaseTLink PulsesNoJoin FlowLink Mode Set ?YesLink Mode SetFigure -NegotiationDecember 200323M9999-120403

元器件交易网8995MFunctional Overview:Switch CoreAddress Look-UpMicrelThe internal look-up table stores MAC addresses and their associated information. It contains a 1K unicast address table plusswitching information. The KS8995M is guaranteed to learn 1K addresses and distinguishes itself from hash-based look-uptables which, depending on the operating environment and probabilities, may not guarantee the absolute number of addressesit can ngThe internal look-up engine will update its table with a new entry if the following conditions are met:•The received packet’s SA (Source Address) does not exist in the look-up table.•The received packet is good; the packet has no receiving errors, and is of legal look-up engine will insert the qualified SA into the table, along with the port number, time stamp. If the table is full, thelast entry of the table will be deleted first to make room for the new ionThe internal look-up engine also monitors whether a station is moved. If it happens, it will update the table ion happens when the following conditions are met:•The received packet’s SA is in the table but the associated source port information is different.•The received packet is good; the packet has no receiving errors, and is of legal look-up engine will update the existing record in the table with the new source port he look-up engine will update the time stamp information of a record whenever the corresponding SA appears. The time stampis used in the aging process. If a record is not updated for a period of time, the look-up engine will remove the record fromthe table. The look-up engine constantly performs the aging process and will continuously remove aging records. The agingperiod is 300 + 75 seconds. This feature can be enabled or disabled through Register 3 or by external pull-up or pull-downresistors on LED[5][2]. See

“Register 3” dingThe KS8995M will forward packets using an algorithm that is depicted in the following flowcharts. Figure 5 shows stage oneof the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table for the destinationaddress, and comes up with “port to forward 1” (PTF1). PTF1 is then further modified by the spanning tree, IGMP snooping,port mirroring, and port VLAN processes to come up with “port to forward 2” (PTF2) as shown in Figure 6. This is where thepacket will be KS8995M will not forward the following packets:•Error packets. These include framing errors, FCS errors, alignment errors, and illegal size packet errors.•802.3x pause frames. The KS8995M will intercept these packets and perform the appropriate actions.•“Local” packets. Based on DA (Destination Address) look-up. If the destination port from the look-up table matchesthe port where the packet was from, the packet is defined as “local.”Switching EngineThe KS8995M features a high-performance switching engine to move data to and from the MAC’s packet buffers. It operatesin store and forward mode, while the efficient switching mechanism reduces overall KS8995M has a 64kB internal frame buffer. This resource is shared between all five ports. The buffer sharing mode canbe programmed through Register 2. See

“Register 2.” In one mode, ports are allowed to use any free buffers in the buffer the second mode, each port is only allowed to use 1/5 of the total buffer pool. There are a total of 512 buffers available. Eachbuffer is sized at (Media Access Controller) OperationThe KS8995M strictly abides by IEEE 802.3 standards to maximize -Packet Gap (IPG)If a frame is successfully transmitted, the 96-bit time IPG is measured between the two consecutive MTXEN. If the currentpacket is experiencing collision, the 96-bit time IPG is measured from MCRS and the next f AlgorithmThe KS8995M implements the IEEE Std 802.3 binary exponential back-off algorithm, and optional “aggressive mode” backoff. After 16 collisions, the packet will be optionally dropped depending on the chip configuration in register 3. See

“Register3.”M9999-12040324December 2003

元器件交易网8995MMicrelStartPTF1=NULLNOVLAN IDVALID?-Search VLAN table-Ingress VLAN filtering-Discard NPVID checkYESSearch PTF1 fromstatic tableFOUNDSearch StaticTableThis search is based onDA or DA+FIDNOTFOUNDSearch PTF1 fromdynamic tableFOUNDDynamicTableSearchThis search is based onDA+FIDNOTFOUNDSearch PTF1 fromVLAN tablePTF1Figure Look-Up Flowchart–Stage 1PTF1Spanning TreeProcess-Check receiving port’s receive enable bit-Check destination port’s transmit enable bit-Check whether packets are special (BPDUor specified)IGMP Process-Applied to MAC #1 to #4-MAC#5 is reserved for microprocessor-IGMP will be forwarded to port 5Port MirrorProcess-RX Mirror-TX Mirror-RX or TX Mirror-RX and TX MirrorPort VLANMembershipCheckPTF2Figure Resolution Flowchart–Stage 2December 200325M9999-120403

元器件交易网8995MMicrelLate CollisionIf a transmit packet experiences collisions after 512-bit times of the transmission, the packet will be l FramesThe KS8995M discards frames less than 64 bytes and can be programmed to accept frames up to 1536 bytes in register special applications, the KS8995M can also be programmed to accept frames up to 1916 bytes in register 4. Since theKS8995M supports VLAN tags, the maximum sizing is adjusted when these tags are ControlThe KS8995M supports standard 802.3x flow control frames on both transmit and receive the receive side, if the KS8995M receives a pause control frame, the KS8995M will not transmit the next normal frame untilthe timer, specified in the pause control frame, expires. If another pause frame is received before the current timer expires,the timer will be updated with the new value in the second pause frame. During this period (being flow controlled), only flowcontrol packets from the KS8995M will be the transmit side, the KS8995M has intelligent and efficient ways to determine when to invoke flow control. The flow controlis based on availability of the system resources, including available buffers, available transmit queues and available KS8995M will flow control a port, which just received a packet, if the destination port resource is being used up. TheKS8995M will issue a flow control frame (XOFF), containing the maximum pause time defined in IEEE standard 802.3x. Oncethe resource is freed up, the KS8995M will send out the other flow control frame (XON) with zero pause time to turn off theflow control (turn on transmission to the port). A hysteresis feature is provided to prevent the flow control mechanism from beingactivated and deactivated too many KS8995M will flow control all ports if the receive queue becomes -Duplex Back PressureA half-duplex back pressure option (note: not in 802.3 standards) is also provided. The activation and deactivation conditionsare the same as the above in full-duplex mode. If back pressure is required, the KS8995M will send preambles to defer theother stations’ transmission (carrier sense deference). To avoid jabber and excessive deference defined in 802.3 standard,after a certain time it will discontinue the carrier sense but it will raise the carrier sense quickly. This short silent time (no carriersense) is to prevent other stations from sending out packets and keeps other stations in carrier sense deferred state. If the porthas packets to send during a back pressure situation, the carrier-sense-type back pressure will be interrupted and thosepackets will be transmitted instead. If there are no more packets to send, carrier-sense-type back pressure will be active againuntil switch resources are free. If a collision occurs, the binary exponential backoff algorithm is skipped and carrier sense isgenerated immediately, reducing the chance of further colliding and maintaining carrier sense to prevent reception of ensure no packet loss in 10BaseT or 100BaseTX half-duplex modes, the user must enable the following:•Aggressive backoff (register 3, bit 0)•No excessive collision drop (register 4, bit 3)•Back pressure (register 4, bit 5)These bits are not set as the default because this is not the IEEE ast Storm ProtectionThe KS8995M has an intelligent option to protect the switch system from receiving too many broadcast packets. Broadcastpackets will be forwarded to all ports except the source port, and thus use too many switch resources (bandwidth and availablespace in transmit queues). The KS8995M has the option to include “multicast packets” for storm control. The broadcast stormrate parameters are programmed globally, and can be enabled or disabled on a per port basis. The rate is based on a 50msinterval for 100BT and a 500ms interval for 10BT. At the beginning of each interval, the counter is cleared to zero, and the ratelimit mechanism starts to count the number of bytes during the interval. The rate definition is described in Register 6 andRegister 7. The default setting for registers 6 and 7 is 0x4A, which is 74 decimal. This is equal to a rate of 1%, calculated asfollows:148,800 frames/sec × 50ms/interval × 1% = 74 frames/interval (approx.) = 0x4AMII Interface OperationThe MII (Media Independent Interface) is specified by the IEEE 802.3 committee and provides a common interface betweenphysical layer and MAC layer devices. The KS8995M provides two such interfaces. The MII-P5 interface is used to connectto the fifth PHY, whereas the MII-SW interface is used to connect to the fifth MAC. Each of these MII interfaces contains twodistinct groups of signals, one for transmission and the other for receiving. Table 5 describes the signals used in the MII-P5interface.M9999-12040326December 2003

元器件交易网8995MMII signalMTXENMTXERMTXD3MTXD2MTXD1MTXD0MTXCMCOLMCRSMRXDVMRXERMRXD3MRXD2MRXD1MRXD0MRXCMDCMDIODescriptionTransmit enableTransmit errorTransmit data bit 3Transmit data bit 2Transmit data bit 1Transmit data bit 0Transmit clockCollision detectionCarrier senseReceive data validReceive errorReceive data bit 3Receive data bit 2Receive data bit 1Receive data bit 0Receive clockManagement data clockManagement data I/OKS8995M signalPMTXENPMTXERPMTXD[3]PMTXD[2]PMTXD[1]PMTXD[0]PMTXCPCOLPCRSPMRXDVPMRXERPMRXD[3]PMRXD[2]PMRXD[1]PMRXD[0]PMRXCMDCMDIOMicrelTable –P5 Signals (PHY Mode)PHY Mode ConnectionExternalMACMTXENMTXERMTXD3MTXD2MTXD1MTXD0MTXCMCOLMCRSMRXDVMRXERMRXD3MRXD2MRXD1MRXD0MRXCKS8995MSignalSMTXENSMTXERSMTXD[3]SMTXD[2]SMTXD[1]SMTXD[0]SMTXCSCOLSCRSSMRXDVNot usedSMRXD[3]SMRXD[2]SMRXD[1]SMRXD[0]SMRXCDescriptionTransmit enableTransmit errorTransmit data bit 3Transmit data bit 2Transmit data bit 1Transmit data bit 0Transmit clockCollision detectionCarrier senseReceive data validReceive errorReceive data bit 3Receive data bit 2Receive data bit 1Receive data bit 0Receive clockMAC Mode ConnectionExternalPHYMTXENMTXERMTXD3MTXD2MTXD1MTXD0MTXCMCOLMCRSMRXDVMRXERMRXD3MRXD2MRXD1MRXD0MRXCKS8995MSignalSMRXDVNot usedSMRXD[3]SMRXD[2]SMRXD[1]SMRXD[0]SMRXCSCOLSCRSSMTXENSMTXERSMTXD[3]SMTXD[2]SMTXD[1]SMTXD[0]SMTXCTable –SW SignalsDecember 200327M9999-120403

元器件交易网8995MMicrelThe MII-P5 interface operates in PHY mode only, while the MII-SW interface operates in either MAC mode or PHY mode. Theseinterfaces are nibble wide data interfaces and therefore run at 1/4 the network bit rate (not encoded). Additional signals on thetransmit side indicate when data is valid or when an error occurs during transmission. Likewise, the receive side has indicatorsthat convey when the data is valid and without physical layer errors. For half-duplex operation there is a signal that indicatesa collision has occurred during that the signal MRXER is not provided on the MII-SW interface for PHY mode operation and the signal MTXER is notprovided on the MII-SW interface for MAC mode operation. Normally MRXER would indicate a receive error coming from thephysical layer device. MTXER would indicate a transmit error from the MAC device. These signals are not appropriate for thisconfiguration. For PHY mode operation, if the device interfacing with the KS8995M has an MRXER pin, it should be tied MAC mode operation, if the device interfacing with the KS8995M has an MTXER pin, it should be tied Interface OperationThe SNI (Serial Network Interface) is compatible with some controllers used for network layer protocol processing. Thisinterface can be directly connected to these types of devices. The signals are divided into two groups, one for transmissionand the other for reception. The signals involved are described in Table SignalTXENTXDTXCCOLCRSRXDRXCDescriptionTransmit enableSerial transmit dataTransmit clockCollision detectionCarrier senseSerial receive dataReceive clockKS8995M SignalSMTXENSMTXD[0]SMTXCSCOLSMRXDVSMRXD[0]SMRXCTable SignalsThis interface is a bit wide data interface and therefore runs at the network bit rate (not encoded). An additional signal on thetransmit side indicates when data is valid. Likewise, the receive side has an indicator that conveys when the data is half-duplex operation there is a signal that indicates a collision has occurred during ed FunctionalitySpanning Tree SupportTo support spanning tree, port 5 is the designated port for the other ports (port 1 - port 4) can be configured in one of the five spanning tree states via “transmit enable,” “receive enable”and “learning disable” register settings in Registers 18, 34, 50, and 66 for ports 1, 2, 3 and 4, respectively. The followingdescription shows the port setting and software actions taken for each of the five spanning tree e state:the port should not forward or receive any packets. Learning is setting:“transmit enable = 0, receive enable = 0, learning disable = 1”Software action:the processor should not send any packets to the port. The switch may still send specific packets to theprocessor (packets that match some entries in the static table with “overriding bit” set) and the processor should discard thosepackets. Note:processor is connected to port 5 via MII interface. Address learning is disabled on the port in this ng state:only packets to the processor are forwarded. Learning is setting:“transmit enable = 0, receive enable = 0, learning disable = 1”Software action:the processor should not send any packets to the port(s) in this state. The processor should program the statictable with the entries that it needs to receive (e.g. BPDU packets). The “overriding” bit should also be set so that the switchwill forward those specific packets to the processor. Address learning is disabled on the port in this ing state:only packets to and from the processor are forwarded. Learning is setting:“transmit enable = 0, receive enable = 0, learning disable = 1”Software action:The processor should program the static MAC table with the entries that it needs to receive (e.g. BPDUpackets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processormay send packets to the port(s) in this state, see

“Special Tagging Mode” section for details. Address learning is disabled onthe port in this state.M9999-12040328December 2003

元器件交易网8995MMicrelLearning state:only packets to and from the processor are forwarded. Learning is setting:“transmit enable = 0, receive enable = 0, learning disable = 0”Software action:The processor should program the static MAC table with the entries that it needs to receive (e.g. BPDUpackets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processormay send packets to the port(s) in this state, see

“Special Tagging Mode” section for details. Address learning is enabled onthe port in this ding state:packets are forwarded and received normally. Learning is setting:“transmit enable = 1, receive enable = 1, learning disable = 0”Software action:The processor should program the static MAC table with the entries that it needs to receive (e.g. BPDUpackets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processormay send packets to the port(s) in this state, see

“Special Tagging Mode” section for details. Address learning is enabled onthe port in this l Tagging ModeThe special tagging mode is designed for spanning tree protocol IGMP snooping and is flexible for use in other special tagging mode, similar to 802.1q, requires software to change network drivers to insert/modify/strip/interpret thespecial tag. This mode is enabled by setting both register 11 bit 0 and register 80-bit 2.802.1q Tag FormatTPID (tag protocol identifier, 0x8100) + TCISpecial Tag FormatSTPID (special tag identifier, 0x8100)+TCI 0x810+4 bit for “port mask”)+ TCITable l Tagging Mode FormatThe STPID will only be seen and used on the port 5 interface, which should be connected to a processor. Packets from theprocessor to the switch should be tagged with STPID and the port mask defined as below:“0001” packet to port 1 only“0010” packet to port 2 only“0100” packet to port 3 only“1000” packet to port 4 only“0011” packet broadcast to port 1 and “1111” packet broadcast to port 1, 2, 3 and 4.“0000” normal tag, will use KS8995M internal look-up result. Normal packets should use this setting. If packets from theprocessors do not have a tag, the KS8995M will treat them as normal packets and an internal look-up will be KS8995M uses a non-zero “port mask” to bypass the look-up result and override any port setting, regardless of port states(blocking, disable, listening, learning). The Table 5 shows the egress rules when dealing with er 200329M9999-120403

元器件交易网8995MIngress Tag Field(0x810+ port mask)Tx Port“Tag Insertion”0Tx Port“Tag Removal”0Egress Action to Tag Field••••MicrelModify tag field to 0x8100Recalculate CRCNo change to TCI if not null VIDReplace VID with ingress (port 5) port VID if null VID(0x810+ port mask)01•(STPID + TCI) will be removed•Padding to 64 bytes if necessary•Recalculate CRC••••••••Modify tag field to 0x8100Recalculate CRCNo change to TCI if not null VIDReplace VID with ingress (port 5) port VID if null VIDModify tag field to 0x8100Recalculate CRCNo change to TCI if not null VIDReplace VID with ingress (port 5) port VID if null VID(0x810+ port mask)10(0x810+ port mask)11Not TaggedDon’t careDon’t careDetermined by the dynamic MAC address tableTable Egress Rules (Processor to Switch Port 5)For packets from regular ports (port 1 - port 4) to port 5, the port mask is used to tell the processor which port the packet wasreceived on, defined as:“0001” from port 1,“0010” from port 2,“0100” from port 3,“1000” from port 4No values other than the previous four defined should be received in this direction in the special mode. Table 6 shows theegress rule for this s PacketsTagged with 0x8100 + TCIEgress Action to Tag Field••••Modify TPID to 0x810 + “port mask,” which indicates source portNo change to TCI, if VID is not nullReplace null VID with ingress port VIDRecalculate CRCNot tagged•Insert TPID to 0x810 + “port mask,” which indicates source port•Insert TCI with ingress port VID•Recalculate CRCTable Egress Rules (Switch to Processor)IGMP SupportThere are two parts involved to support IGMP in layer 2. The first part is “IGMP” snooping. The switch will trap IGMP packetsand forward them only to the processor port. The IGMP packets are identified as IP packets (either Ethernet IP packets or IEEE802.3 SNAP IP packets) AND IP version = 0x4 AND protocol number = 0x2. The second part is “multicast address insertion”in the static MAC table. Once the multicast address is programmed in the static MAC table, the multicast session will be trimmedto the subscribed ports, instead of broadcasting to all ports. To enable this feature, set register 5 bit 6 to 1. Also “special tagmode” needs to be enabled, so that the processor knows which port the IGMP packet was received on. Enable “special tagmode” by setting both register 11 bit 0 and register 80-bit 2.M9999-12040330December 2003

元器件交易网8995MPort Mirroring SupportMicrelKS8995M supports “port mirror” comprehensively as:1.“Receive Only” mirror on a port. All the packets received on the port will be mirrored on the sniffer port. For example,port 1 is programmed to be “rx sniff,” and port 5 is programmed to be the “sniffer port.” A packet, received on port1, is destined to port 4 after the internal look-up. The KS8995M will forward the packet to both port 4 and port 8995M can optionally forward even “bad” received packets to port 5.2.“Transmit Only” mirror on a port. All the packets transmitted on the port will be mirrored on the sniffer port. Forexample, port 1 is programmed to be “tx sniff,” and port 5 is programmed to be the “sniffer port.” A packet, receivedon any of the ports, is destined to port 1 after the internal look-up. The KS8995M will forward the packet to both port1 and port 5.3.“Receive and Transmit” mirror on two ports. All the packets received on port A AND transmitted on port B will bemirrored on the sniffer port. To turn on the “AND” feature, set register 5 bit 0 to 1. For example, port 1 is programmedto be “rx sniff,” port 2 is programmed to be “transmit sniff” and port 5 is programmed to be the “sniffer port.” A packet,received on port 1, is destined to port 4 after the internal look-up. The KS8995M will forward the packet to port 4 only,since it does not meet the “AND” condition. A packet, received on port 1, is destined to port 2 after the internal look-up. The KS8995M will forward the packet to both port 2 and port le ports can be selected to be “rx sniffed” or “tx sniffed.” And any port can be selected to be the “sniffer port.” All theseper port features can be selected through Register SupportKS8995M supports 16 active VLANs out of 4096 possible VLANs specified in IEEE 802.1q. KS8995M provides a 16-entryVLAN table, which converts VID (12 bits) to FID (4bits) for address look-up. If a non-tagged or null-VID-tagged packet isreceived, the ingress port VID is used for look-up. In the VLAN mode, the look-up process starts with VLAN table look-up todetermine whether the VID is valid. If the VID is not valid, the packet will be dropped and its address will not be learned. Ifthe VID is valid, FID is retrieved for further look-up. FID+DA is used to determine the destination port. FID+SA is used forlearning found inStatic MAC tableNoNoYesYesYesYesDA+FID found inDynamic MAC tableNoYesDon’t careNoYesDon’t careUSE FID Flag?Don’t careDon’t care0111FID Match?Don’t careDon’t careDon’t careNoNoYesActionBroadcast to the membership ports defined in theVLAN table bit[20:16]Send to the destination port defined in thedynamic MAC table bit[54:52]Send to the destination port(s) defined in thestatic MAC table bit[52:48]Broadcast to the membership ports defined inthe VLAN table bit[20:16]Send to the destination port defined in thedynamic MAC table bit[54:52]Send to the destination port(s) defined in thestatic MAC table bit[52:48]Table +DA Look-Up in the VLAN ModeDecember 200331M9999-120403

元器件交易网8995MSA+FID found inDynamic MAC tableNoYesActionThe SA+FID will be learned into the dynamic stamp will be updatedMicrelTable +SA Look-Up in the VLAN ModeAdvanced VLAN features are also supported in KS8995M, such as “VLAN ingress filtering” and “discard non PVID” definedin register 18 bit 6 and bit 5. These features can be controlled on a port Limit SupportKS8995M supports hardware rate limiting on “receive” and “transmit” independently on a per port basis. It also supports ratelimiting in a priority or non-priority environment. The rate limit starts from 0Kbps and goes up to the line rate in steps of KS8995M uses one second as an interval. At the beginning of each interval, the counter is cleared to zero, and the ratelimit mechanism starts to count the number of bytes during this receive, if the number of bytes exceeds the programmed limit, the switch will stop receiving packets on the port until the“one second” interval expires. There is an option provided for flow control to prevent packet loss. If the rate limit is programmedgreater than or equal to 128Kbps and the byte counter is 8K bytes below the limit, the flow control will be triggered. If the ratelimit is programmed lower than 128Kbps and the byte counter is 2K bytes below the limit, the flow control will be transmit, if the number of bytes exceeds the programmed limit, the switch will stop transmitting packets on the port untilthe “one second” interval priority is enabled, the KS8995M can support different rate controls for both high priority and low priority packets. This canbe programmed through registers 21–27.M9999-12040332December 2003

元器件交易网8995MConfiguration InterfaceMicrelThe KS8995M can function as a managed switch or unmanaged switch. If no EEPROM or micro-controller exists, theKS8995M will operate from its default setting. Some default settings are configured via strap in options as indicated in the #14546Pin NameTEST1MUX1MUX2PU/PDNCNCNCDescriptionNC for normal operation. Factory test 1 and MUX2 should be left unconnected for normal are factory test pinsModeNormal OperationRemote Analog Loopback Mode for Testing onlyReservedPower Save Mode for Testing only626364656667PMRXD3PMRXD2PMRXD1PMRXD0PMRXERPCRSIpd/OIpd/OIpd/OIpd/OIpd/OIpd/OMux1NC011Mux2NC101PHY[5] MII receive bit 3. Strap option:PD (default) = enable flow control;PU = disable flow [5] MII receive bit 2. Strap option:PD (default) = disable back pressure;PU = enable back [5] MII receive bit 1. Strap option:PD (default) = drop excessive collisionpackets; PU = does not drop excessive collision [5] MII receive bit 0. Strap option:PD (default) = disable aggressive back-offalgorithm in half-duplex mode; PU = enable for performance [5] MII receive error. Strap option:PD (default) = 1522/1518 bytes;PU = packet size up to 1536 [5] MII carrier sense/Force duplex mode. See

“Register 76” for port 4 (default) = Force half-duplex if auto-negotiation is disabled or fails. PU = Forcefull-duplex if auto-negotiation is disabled or [5] MII collision detect/ Force flow control. See

“Register 66” for port 4 (default) = No force flow control. PU = Force flow MII receive bit 3. Strap option:PD (default) = Disable Switch MII full-duplexflow control; PU = Enable Switch MII full-duplex flow MII receive bit 2. Strap option:PD (default) = Switch MII in full-duplex mode;PU = Switch MII in half-duplex MII receive bit 1. Strap option:PD (default) = Switch MII in 100Mbps mode;PU = Switch MII in 10Mbps MII receive bit 0; Strap option: LED Mode PD (default) = Mode 0;PU = Mode 1. See

“Register 11.”Mode 0LEDX_2LEDX_1LEDX_0Lnk/ActFulld/ColSpeedMode 1100Lnk/Act10Lnk/ActFulld6880818283PCOLSMRXD3SMRXD2SMRXD1SMRXD0Ipd/OIpd/OIpd/OIpd/OIpd/ODecember 200333M9999-120403

元器件交易网8995MPin #86Pin NameSCONF1PU/PDIpdDescriptionDual MII configuration # (91, 86, 87):179091113SCONF0LED5-2LED5-1PS1IpdIpu/OIpu/OIpdSwitch MIIDisable, OtriPHY Mode MIIMAC Mode MIIPHY Mode SNIDisablePHY Mode MIIMAC Mode MIIPHY Mode SNIPHY [5] MIIDisable, OtriDisable, OtriDisable, OtriDisable, OtriDisablePHY Mode MIIPHY Mode MIIPHY Mode MIIMicrelDual MII configuration indicator 2. Strap option: Aging setup. See

“Aging” (default) = Aging Enable; PD = Aging indicator 1. Strap option:PU (default): enable PHY MII I/F. PD:tristate all PHYMII output. See

“pin# 86 SCONF1.”Serial bus configuration pinIf EEPROM is not present, the KS8995M will start itself with chipdefault (00)...Pin ConfigurationPS[1:0]=00PS[1:0]=01PS[1:0]=10PS[1:0]=11Serial Bus ConfigurationI2C Master Mode for EEPROMReservedSPI Slave Mode for CPU InterfaceFactory Test Mode (BIST)114128PS0TEST2IpdNCSerial bus configuration pin. See

“pin# 113.”NC for normal operation. Factory test pin.M9999-12040334December 2003

元器件交易网8995MMicrelI2C Master Serial Bus ConfigurationIf a 2-wire EEPROM exists, the KS8995M can perform more advanced features like “broadcast storm protection,” “rate control,”etc. The EEPROM should have the entire valid configuration data from register 0 to register 109 defined in the

“Memory Map,”except the status registers. After reset, the KS8995M will start to read all 110 registers sequentially from the EEPROM. Theconfiguration access time (tprgm) is less than 15ms as shown in Figure _prgm<15 msFigure 8995M EEPROMConfiguration Timing DiagramTo configure the KS8995M with a pre-configured EEPROM use the following steps:1. At the board level, connect pin 110 on the KS8995M to the SCL pin on the EEPROM. Connect pin 111 on theKS8995M to the SDA pin on the EEPROM.2. Set the input signals PS[1:0] (pins 113 and 114, respectively) to “00”. This puts the KS8995M serial bus configurationinto I2C master mode.3. Be sure the board level reset signal is connected to the KS8995M reset signal on pin 115 (RST_N).4. Program the contents of the EEPROM before placing it on the board with the desired configuration data. Note thatthe first byte in the EEPROM must be “95” for the loading to occur properly. If this value is not correct, all other datawill be ignored.5. Place EEPROM on the board and power up the board. Assert the active-low board level reset to RST_N on theKS8995M. After the reset is deasserted, the KS8995M will begin reading configuration data from the EEPROM. Theconfiguration access time (tprgm) is less than : For proper operation, make sure pin 47 (PWRDN_N) is not asserted during the reset Slave Serial Bus ConfigurationThe KS8995M can also act as an SPI slave device. Through the SPI, the entire feature set can be enabled, including “VLAN,”“IGMP snooping,” “MIB counters,” etc. The external master device can access any register from register 0 to register 127randomly. The system should configure all the desired settings before enabling the switch in the KS8995M. To enable theswitch, write a one to register 1 bit standard SPI commands are supported (00000011 for “READ DATA,” and 00000010 for “WRITE DATA”). To speedconfiguration time, the KS8995M also supports multiple reads or writes. After a byte is written to or read from the KS8995M,the internal address counter automatically increments if the SPI Slave Select signal (SPIS_N) continues to be driven low. IfSPIS_N is kept low after the first byte is read, the next byte at the next address will be shifted out on SPIQ. If SPIS_N is keptlow after the first byte is written, bits on the Master Out Slave Input (SPID) line will be written to the next address. AssertingSPIS_N high terminates a read or write operation. This means that the SPIS_N signal must be asserted high and then low againbefore issuing another command and address. The address counter wraps back to zero once it reaches the highest ore the entire register set can be written to or read from by issuing a single command and KS8995M is able to support a 5MHz SPI bus. A high performance SPI master is recommended to prevent internal er 200335M9999-120403

元器件交易网8995MTo use the KS8995M SPI:1. At the board level, connect KS8995M pins as follows:KS8995MPin Number9KS8995MSignal NameSPIS_NSPICSPIDSPIQMicroprocessor SignalDescriptionSPI Slave SelectSPI ClockMaster Out Slave InputMaster In Slave OutputMicrelTable Connections2. Set the input signals PS[1:0] (pins 113 and 114 respectively) to “10” to set the serial configuration to SPI slave mode.3. Power up the board and assert a reset signal. After reset, the start switch bit in register 1 will be set to ‘0’. Configurethe desired settings in the KS8995M before setting the start register to ‘1’.4. Write configuration to registers using a typical SPI write data cycle as shown in Figure 8 or SPI multiple write as shownin Figure 10. Note that data input on SPID is registered on the rising edge of SPIC.5. Registers can be read and configuration can be verified with a typical SPI read data cycle as shown in Figure 9 ora multiple read as shown in Figure 11. Note that read data is registered out of SPIQ on the falling edge of SPIC.6. After configuration is written and verified, write a ‘1’ to register 1 bit 0 to begin KS8995M operation.M9999-12040336December 2003

元器件交易网8995MMicrelSPIS_NSPICSPIDSPIQX00000010A7A6A5A4A3A2A1A0D7D6D5D4D3D2D1D0WRITE COMMANDWRITE ADDRESSWRITE DATAFigure Write Data CycleSPIS_NSPICSPIDSPIQX00000011A7A6A5A4A3A2A1A0D7D6D5D4D3D2D1D0READ COMMANDREAD ADDRESSREAD DATAFigure Read Data CycleDecember 200337M9999-120403

元器件交易网8995MMicrelSPIS_NSPICSPIDSPIQX00000010A7A6A5A4A3A2A1A0D7D6D5D4D3D2D1D0WRITE COMMANDSPIS_NSPICSPIDSPIQD7D6D5D4D4D2D1D0D7D6D5WRITE ADDRESSByte 1D4D3D2D1D0D7D6D5D4D3D2D1D0Byte 2Byte 3 ...Byte NFigure Multiple WriteSPIS_NSPICSPIDSPIQX00000011A7A6A5A4A3A2A1A0XD7XD6XD5XD4XD3XD2XD1XD0READ COMMANDSPIS_NSPICSPIDSPIQXD7READ ADDRESSByte 1XD6XD5XD4XD3XD2XD1XD0XD7XD6XD5XD4XD3XD2XD1XD0XD7XD6XD5XD4XD3XD2XD1XD0Byte 2Byte 3Byte NFigure Multiple ReadMII Management Interface (MIIM)A standard MIIM interface is provided for all five PHY devices in the KS8995M. An external device with MDC/MDIO capabilityis able to read PHY status or to configure PHY settings. For details on the MIIM interface standard please reference the IEEE802.3 specification (section 22.2.4.5). The MIIM interface does not have access to all the configuration registers in theKS8995M. It can only access the standard MII registers. See

“MIIM Registers.” The SPI interface, on the other hand, can beused to access the entire KS8995M feature set.M9999-12040338December 2003

元器件交易网8995MRegister Description OffsetDecimal0-12-1112-1516-2930-3132-4546-4748-6162-6364-7778-7980-9394-9596-103104-109110-111112-120121-122123-124125-126127Hex0x00-0x010x02-0x0B0x0C-0x0F0x10-0x1D0x1E-0x2F0x20-0x2D0x2E-0x2F0x30-0x3D0x3E-0x3F0x40-0x4D0x4E-0x4F0x50-0x5D0x5E-0x5F0x60-0x670x68-0x6D0x6E-0x6F0x70-0x780x79-0x7A0x7B-0x7C0x7D-0x7E0x7FDescriptionChip ID RegistersGlobal Control RegistersReservedPort 1 Control RegistersPort 1 Status RegistersPort 2 Control RegistersPort 2 Status RegistersPort 3 Control RegistersPort 3 Status RegistersPort 4 Control RegistersPort 4 Status RegistersPort 5 Control RegistersPort 5 Status RegistersTOS Priority Control RegistersMAC Address RegistersIndirect Access Control RegistersIndirect Data RegistersDigital Testing Status RegistersDigital Testing Control RegistersAnalog Testing Control RegistersAnalog Testing Status RegisterMicrelGlobal RegistersAddressNameDescriptionModeDefaultRegister 0 (0x00): Chip ID07-0Family IDChip familyRO0x95Register 1 (0x01): Chip ID1 / Start Switch7-43-10Chip IDRevision IDStart Switch0x0 is assigned to M series. (95M)Revision ID1, start the chip when external pins (PS1, PS0) = (1,0)or (0,1). Note: in (PS1,PS0) = (0,0) mode, the chip willstart automatically, after trying to read the externalEEPROM. If EEPROM does not exist, the chip will usedefault values for all internal registers. If EEPROM ispresent, the contents in the EEPROM will be switch will check: (1) Register 0 = 0x95,(2) Register 1 [7:4] = 0x0. If this check is OK, thecontents in the EEPROM will override chip registerdefault values.=0, chip will not start when external pins(PS1, PS0) = (1,0) or (0,1).Note: (PS1, PS0) = (1,1) for factory test 0x00x20x0December 200339M9999-120403

元器件交易网8995MAddressNameDescriptionModeDefaultRegister 2 (0x02): Global Control 076-4Reserved802.1p base priorityReservedUsed to classify priority for incoming 802.1q packets.“User priority” is compared against this value.≥ : classified as high priority.< : classified as low priority.1, enable PHY MII interface.(Note: if not enabled, the switch will tri-state all outputs)R/WR/W0x00x4Micrel3Enable PHY MIIR/WPin LED[5][1]strap -down (0):isolate. Pull-up(1)::LED[5][1]has internalpull-up.0x12Buffer share mode1, buffer pool is shared by all ports. A port can usemore buffer when other ports are not busy.0, a port is only allowed to use 1/5 of the buffer pool.1 the switch will drop packets with 0x8808 in T/Lfiled, or DA=01-80-C2-00-00-01.0, the switch will drop packets qualified as“flow control” packets.1, link change from “link” to “no link” will cause fastaging (<800µs) to age address table faster. After anage cycle is complete, the age logic will return tonormal (300 + 75 seconds ). Note: If any port isunplugged, all addresses will be automatically agedout.R/W1UNH modeR/W00Link change ageR/W0Register 3 (0x03): Global Control 17Pass all frames1, switch all packets including bad ones. Used solelyfor debugging purpose. Works in conjunction withsniffer ed0, will enable transmit flow control based on AN result.1, will not enable transmit flow control regardless ofAN result.R/W065ReservedIEEE 802.3x Transmitflow control disableR/WR/W0Pin PMRXD3strap -down(0):Enable tx flowcontrol. Pull-up (1):Disable tx/rxflow :PMRXD3has internal PMRXD3 strapoption. Pull-down(0):Enable rx flowcontrol. Pull-up (1):Disable tx/rx :PMRXD3has internal pull-down.04IEEE 802.3x Receiveflow control disable0, will enable receive flow control based on AN result.1, will not enable receive flow control regardless ofAN : Bit 5 and bit 4 default values are controlled bythe same pin, but they can be programmedindependently.R/W3Frame Length field check1, will check frame length field in the IEEE the actual length does not match, the packet will bedropped. (for L/T < 1500)R/WM9999-12040340December 2003

元器件交易网8995MAddress2NameAging enableDescription1, Enable age function in the chip0, Disable aging functionModeR/WDefaultMicrelPin LED[5][2] strapoption. Pull-down(0): Aging -up (1):: LED[5][2]has internal pullup.0Pin PMRXD0 strapoption. Pull-down(0):Disableaggressive backoff. Pull-up (1):Aggressive : PMRXD0has internal pulldown.10Fast age enableAggressive backoff enable1, Turn on fast age (800µs)1, Enable more aggressive backoff algorithm in halfduplex mode to enhance performance. This is not anIEEE standard.R/WR/WRegister 4 (0x04): Global Control 27Unicast port-VLANmismatch discardThis feature is used for port-VLAN.(described in reg17, )1, all packets can not cross VLAN boundary.0, unicast packets (excluding unknown/mutlicast/broadcast) can cross VLAN boundary.1, “Broadcast Storm Protection” does not includemulticast packets. Only DA=FFFFFFFFFFFF packetswill be regulated.0, “Broadcast Storm Protection” includes DA =FFFFFFFFFFFF and DA[40] = 1 packets.1, carrier sense based backpressure is selected.0, collision based backpressure is selected.1, fair mode is selected. In this mode, if a flow controlport and a non-flow control port talk to the samedestination port, packets from the non-flow control portmay be dropped. This is to prevent the flow control portfrom being flow controlled for an extended period of time.0, in this mode, if a flow control port and a non-flowcontrol port talk to the same destination port, the flowcontrol port will be flow controlled. This may not be “fair”to the flow control port.1, the switch will not drop packets when 16 or morecollisions occur.0, the switch will drop packets when 16 or morecollisions occur.R/W16Multicast Stormprotection disableR/W154Back pressure modeFlow control and backpressure fair modeR/WR/W113No excessive collision dropR/WPin PMRXD1 strapoption. Pull-down(0): Dropexcessive collisionpackets. Pull-up (1):Don’t dropexcessive :PMRXD1has internal pulldown.02Huge packet support1, will accept packet sizes up to 1916 bytes (inclusive).This bit setting will override setting from bit 1 of thesame register.0, the max packet size will be determined by bit 1 of thisregister.R/WDecember 200341M9999-120403

元器件交易网8995MAddress1NameLegal Maximum Packetsize check disableDescription1, will accept packet sizes up to 1536 bytes (inclusive).0, 1522 bytes for tagged packets (not including packetswith STPID from CPU to ports 1-4), 1518 bytes foruntagged packets. Any packets larger than the specifiedvalue will be /WDefaultMicrelPin PMRXERstrap -down (0):1518/1522 bytepackets. Pull-up(1): 1536 :PMRXERhas internal pulldown.00Priority Buffer reserve1, Each output queue is pre-allocated 48 buffers,used exclusively for high priority packets. It isrecommended to enable this when priority queuefeature is turned on.0, No reserved buffers for high priority packets.R/WRegister 5 (0x05): Global Control 37802.1q VLAN enable1, 802.1q VLAN mode is turned on. VLAN table needsto set up before the operation.0, 802.1q VLAN is disabled.1, IGMP snoop enabled. All the IGMP packets will beforwarded to switch MII port.0, IGMP snoop disabled.1, direct mode on port 5. This is a special mode for theswitch MII interface. Using preamble before MRXDV todirect switch to forward packets, bypassing internallook-up.0, normal operation.1, packets forwarded to switch MII interface will bepre-tagged with the source port number.(preamble before MRXDV)0, normal operation.00 = always deliver high priority packets first.01 = deliver high/low packets at ratio 10/1.10 = deliver high/low packets at ratio 5/1.11 = deliver high/low packets at ratio 2/1.1, the last 5 digits in the VID field are used as a maskto determine which port(s) the packet should beforwarded to.0, no tag masks.1, will do Rx AND Tx sniff (both source port anddestination port need to match).0, will do Rx OR Tx sniff (Either source port ordestination port needs to match). This is the modeused to implement Rx only sniff.R/W06IGMP snoop enable onSwitch MII interfaceEnable direct mode onSwitch MII interfaceR/W05R/W04Enable pre tag onSwitch MII interfaceR/W03-2Priority Scheme selectR/W001Enable “tag” maskR/W00Sniff mode selectR/W0Register 6 (0x06): Global Control 47Switch MII backpressure enableSwitch MII halfduplex mode1, enable half-duplex back pressure on switch MIIinterface.0, disable back pressure on switch MII interface.1, enable MII interface half-duplex mode.0, enable MII interface full-duplex mode.R/W06R/WPin SMRXD2 strapoption. Pull-down(0): Full duplexmode. Pull-up(1):Half duplexmode

Note:SMRXD2 hasinternal pull down.M9999-12040342December 2003

元器件交易网8995MAddress5NameSwitch MII flowcontrol enableDescription1, enable full-duplex flow control on switch MII interface.0, disable full-duplex flow control on switch MII /WDefaultMicrelPin SMRXD3 strapoption. Pull-down(0):disable flowcontrol. Pull-up(1):enable flow : SMRXD3has internal SMRXD1 strapoption. Pull-down(0):Enable100Mbps. Pull-up(1):Enable :SMRXD1has internal pull-down.00004Switch MII 10BT1, the switch interface is in 10Mbps mode.0, the switch interface is in 100Mbps mode.R/W32-0Null VID replacementBroadcast stormprotection rate Bit [10:8]1, will replace null VID with port VID(12 bits).0, no replacement for null along with the next register determines how many“64 byte blocks” of packet data allowed on an input portin a preset period. The period is 50ms for 100BT or500ms for 10BT. The default is 1%.R/WR/WRegister 7 (0x07): Global Control 57-0Broadcast stormprotection rate Bit [7:0]This along with the previous register determines howmany “64 byte blocks” of packet data are allowed on aninput port in a preset period. The period is 50ms for100BT or 500ms for 10BT. The default is 1%.R/W0x4A(1)Note:1.148,800 frames/sec × 50ms/interval × 1% = 74 frames/interval (approx.) = 0x4ARegister 8 (0x08): Global Control 67-0Factory testingReservedR/W0x24Register 9 (0x09): Global Control 77-0Factory testingReservedR/W0x28Register 10 (0x0A): Global Control 87-0Factory testingReservedR/W0x24Register 11 (0x0B): Global Control 97-21ReservedLED modeN/A0 = led mode 01 = led mode 1R/W0Pin SMRXD0 strapoption. Pull-down(0):Enabled ledmode 0. Pull-up(1):Enabled led mode :SMRXD0 hasinternal pull-down 0LEDX_2LEDX_1LEDX_00Special TPID modeLnk/ActFulld/ColSpeedMode 1100Lnk/Act10Lnk/ActFulldR/W0Used for direct mode forwarding from port

“Spanning Tree” functional er 200343M9999-120403

元器件交易网8995MPort RegistersMicrelThe following registers are used to enable features that are assigned on a per port basis. The register bit assignments arethe same for all ports, but the address for each port is different, as er 16 (0x10): Port 1 Control 0Register 32 (0x20): Port 2 Control 0Register 48 (0x30): Port 3 Control 0Register 64 (0x40): Port 4 Control 0Register 80 (0x50): Port 5 Control 0Address7NameBroadcast stormprotection enableDiffserv priorityclassification enable802.1p priorityclassification enablePort-based priorityclassification enableDescription1, enable broadcast storm protection for ingress packetson the port.0, disable broadcast storm protection.1, enable DiffServ priority classification for ingresspackets on port.0, disable DiffServ function.1, enable 802.1p priority classification for ingresspackets on port.0, disable 802.1p.1, ingress packets on the port will be classified as highpriority if “DiffServ” or “802.1p” classification is notenabled or fails to classify.0, ingress packets on port will be classified as low priorityif “DiffServ” or “802.1p” classification is not enabled orfails to :“DiffServ”, “802.1p” and port priority can beenabled at the same time. The OR’ed result of 802.1pand DSCP overwrites the port ed1, when packets are output on the port, the switch willadd 802.1q tags to packets without 802.1q tags whenreceived. The switch will not add tags to packets alreadytagged. The tag inserted is the ingress port’s “port VID”0, disable tag insertion.1, when packets are output on the port, the switch willremove 802.1q tags from packets with 802.1q tagswhen received. The switch will not modify packetsreceived without tags.0, disable tag removal.1, the port output queue is split into high and lowpriority queues.0, single output queue on the port. There is no prioritydifferentiation even though packets are classified intohigh or low /WDefault06R/W05R/W04R/W032ReservedTag insertionR/WR/W001Tag removalR/W00Priority enableR/W0Register 17 (0x11): Port 1 Control 1Register 33 (0x21): Port 2 Control 1Register 49 (0x31): Port 3 Control 1Register 65 (0x41): Port 4 Control 1Register 81 (0x51): Port 5 Control 1Address7NameSniffer portDescription1, Port is designated as sniffer port and will transmitpackets that are monitored.0, Port is a normal port.1, All the packets received on the port will be markedas “monitored packets” and forwarded to the designated“sniffer port.”0, no receive /WDefault06Receive sniffR/W0M9999-12040344December 2003

元器件交易网8995MAddress5NameTransmit sniffDescription1, All the packets transmitted on the port will bemarked as “monitored packets” and forwarded to thedesignated “sniffer port.”0, no transmit the port’s “Port VLAN membership.” Bit 4 standsfor port 5, bit 3 for bit 0 for port 1. The Port canonly communicate within the membership. A ‘1’includes a port in the membership, a ‘0’ excludes a portfrom /WDefault0Micrel4-0Port VLAN membershipR/W0x1fRegister 18 (0x12): Port 1 Control 2Register 34 (0x22): Port 2 Control 2Register 50 (0x32): Port 3 Control 2Register 66 (0x42): Port 4 Control 2Register 82 (0x52): Port 5 Control 2Address76NameReservedIngress VLAN filteringDescriptionReserved1, the switch will discard packets whose VID portmembership in VLAN table bit[20:16] does not includethe ingress port.0, no ingress VLAN filtering.1, the switch will discard packets whose VID doesnot match ingress port default VID.0, no packets will be discarded.1, will always enable rx and tx flow control on the port,regardless of AN result.0, the flow control is enabled based on AN : Setting a port for both half-duplex and forcedflow control is an illegal configuration. For half-duplexenable back pressure.R/WModeDefault0x005Discard Non PVID packetsR/W04Force flow controlR/W0For port 4 only,there is a specialconfiguration pinto set the default,Pin PCOL strapoption. Pull-down(0):No Force flowcontrol Pull-up(1):Force : PCOL hasinternal pull PMRXD2 strapoption. Pull-down(0):disable backpressure. Pull-up(1):enable : PMRXD2 hasinternal pull-down.1103Back pressure enable1, enable port’s half-duplex back pressure.0, disable port’s half-duplex back pressure.R/W210Note:Transmit enableReceive enableLearning disable1, enable packet transmission on the port.0, disable packet transmission on the port.1, enable packet reception on the port.0, disable packet reception on the port.1, disable switch address learning capability.0, enable switch address learning.R/WR/WR/WBits 2-0 are used for spanning tree support. See

“Spanning Tree Support”

er 200345M9999-120403

元器件交易网8995MRegister 19 (0x13): Port 1 Control 3Register 35 (0x23): Port 2 Control 3Register 51 (0x33): Port 3 Control 3Register 67 (0x43): Port 4 Control 3Register 83 (0x53): Port 5 Control 3Address7-0NameDefault tag [15:8]DescriptionPort’s default tag, containing7-5:user priority bits4: CFI bit3-0 : VID[11:8]ModeR/WDefault0MicrelRegister 20 (0x14): Port 1 Control 4Register 36 (0x24): Port 2 Control 4Register 52 (0x34): Port 3 Control 4Register 68 (0x44): Port 4 Control 4Register 84 (0x54): Port 5 Control 4Address7-0NameDefault tag [7:0]DescriptionDefault port 1’s tag, containing7-0: VID[7:0]ModeR/WDefault1Note:Registers 19 and 20 (and those corresponding to other ports) serve two purposes:(1) Associated with the ingress untagged packets, and used foregress tagging; (2) Default VID for the ingress untagged or null-VID-tagged packets, and used for address er 21 (0x15): Port 1 Control 5Register 37 (0x25): Port 2 Control 5Register 53 (0x35): Port 3 Control 5Register 69 (0x45): Port 4 Control 5Register 85 (0x55): Port 5 Control 5Address7-0NameTransmit high priorityrate control [7:0]DescriptionThis along with port control 7, bits [3:0] form a 12-bitfield to determine how many “32Kbps” high priorityblocks can be transmitted. (In a unit of 4K bytes in aone second period.)ModeR/WDefault0Register 22 (0x16): Port 1 Control 6Register 38 (0x26): Port 2 Control 6Register 54 (0x36): Port 3 Control 6Register 70 (0x46): Port 4 Control 6Register 86 (0x56): Port 5 Control 6Address7-0NameTransmit low priorityrate control [7:0]DescriptionThis along with port control 7, bits [7:4] form a 12-bitfield to determine how many “32Kbps” low priorityblocks can be transmitted. (In a unit of 4K bytes in aone second period.)ModeR/WDefault0Register 23 (0x17): Port 1 Control 7Register 39 (0x27): Port 2 Control 7Register 55 (0x37): Port 3 Control 7Register 71 (0x47): Port 4 Control 7Register 87 (0x57): Port 5 Control 7Address7-4NameTransmit low priorityrate control [11:8]DescriptionThis along with port control 6, bits [7:0] form a 12-bitfield to determine how many “32Kbps” low priorityblocks can be transmitted. (In a unit of 4K bytes in aone second period.)This along with port control 5, bits [7:0] form a 12-bitfield to determine how many “32Kbps” high priorityblocks can be transmitted. (In unit of 4K bytes in aone second period.)ModeR/WDefault03-0Transmit high priorityrate control [11:8]R/W0M9999-12040346December 2003

元器件交易网8995MRegister 24 (0x18): Port 1 Control 8Register 40 (0x28): Port 2 Control 8Register 56 (0x38): Port 3 Control 8Register 72 (0x48): Port 4 Control 8Register 88 (0x58): Port 5 Control 8Address7-0NameReceive high priorityrate control [7:0]DescriptionThis along with port control 10, bits [3:0] form a 12-bitfield to determine how many “32Kbps” high priorityblocks can be received. (In a unit of 4K bytes in a onesecond period.)ModeR/WDefault0MicrelRegister 25 (0x19): Port 1 Control 9Register 41 (0x29): Port 2 Control 9Register 57 (0x39): Port 3 Control 9Register 73 (0x49): Port 4 Control 9Register 89 (0x59): Port 5 Control 9Address7-0NameReceive low priorityrate control [7:0]DescriptionThis along with port control 10, bits [7:4] form a 12-bitfield to determine how many “32Kbps” low priorityblocks can be received. (In a unit of 4K bytes in a onesecond period.)ModeR/WDefault0Register 26 (0x1A): Port 1 Control 10Register 42 (0x2A): Port 2 Control 10Register 58 (0x3A): Port 3 Control 10Register 74 (0x4A): Port 4 Control 10Register 90 (0x5A): Port 5 Control 10Address7-4NameReceive low priorityrate control [11:8]DescriptionThis along with port control 9, bits [7:0] form a 12-bitfield to determine how many “32Kbps” low priorityblocks can be received. (In a unit of 4K bytes in a onesecond period.)This along with port control 8, bits [7:0] form a 12-bitfield to determine how many “32Kbps” high priorityblocks can be received. (In a unit of 4K bytes in a onesecond period.)ModeR/WDefault03-0Receive high priorityrate control [11:8]R/W0Register 27 (0x1B): Port 1 Control 11Register 43 (0x2B): Port 2 Control 11Register 59 (0x3B): Port 3 Control 11Register 75 (0x4B): Port 4 Control 11Register 91 (0x5B): Port 5 Control 11Address7NameReceive differentialpriority rate controlDescription1, If bit 6 is also ‘1’ this will enable receive rate controlfor this port on low priority packets at the low priorityrate. If bit 5 is also ‘1’, this will enable receive ratecontrol on high priority packets at the high priority rate0, receive rate control will be based on the low priorityrate for all packets on this port.1, enable port’s low priority receive rate control feature.0, disable port’s low priority receive rate control.1, If bit 7 is also ‘1’ this will enable the port’s highpriority receive rate control feature. If bit 7 is a ‘0’ andbit 6 is a ‘1’, all receive packets on this port will be ratecontrolled at the low priority rate.0, disable port’s high priority receive rate control feature.1, flow control may be asserted if the port’s low priorityreceive rate is exceeded.0, flow control is not asserted if the port’s low priorityreceive rate is /WDefault065Low priority receiverate control enableHigh priority receiverate control enableR/WR/W004Low priority receive rateflow control enableR/W0December 200347M9999-120403

元器件交易网8995MAddress3NameHigh priority receiverate flow control enableDescription1, flow control may be asserted if the port’s highpriority receive rate is exceeded. (To use this, differentialreceive rate control must be on.)0, flow control is not asserted if the port’s highpriority receive rate is exceeded.1, will do transmit rate control on both high and lowpriority packets based on the rate counters defined bythe high and low priority packets respectively.0, will do transmit rate control on any rate counters defined in low priority will be used.1, enable the port’s low priority transmit rate controlfeature.0, disable the port’s low priority transmit rate controlfeature.1, enable the port’s high priority transmit rate controlfeature.0, disable the port’s high priority transmit rate /WDefault0Micrel2Transmit differentialpriority rate controlR/W01Low priority transmitrate control enableR/W00High priority transmitrate control enableR/W0Register 28 (0x1C): Port 1 Control 12Register 44 (0x2C): Port 2 Control 12Register 60 (0x3C): Port 3 Control 12Register 76 (0x4C): Port 4 Control 12Register 92 (0x5C): Port 5 Control 12Note:Port Control 12 and 13, and Port Status 0 contents can be accessed by MIIM (MDC/MDIO) interface via the standard MIIM register s7NameDisable auto-negotiationDescription1, disable auto-negotiation, speed and duplex aredecided by bit 6 and 5 of the same register.0, auto-negotiation is on.1, forced 100BT if AN is disabled (bit 7).0, forced 10BT if AN is disabled (bit 7).1, forced full-duplex if (1) AN is disabled or (2) AN isenabled but failed.0, forced half-duplex if (1) AN is disabled or (2) AN isenabled but /WDefault065Forced speedForced duplexR/WR/W10For port 4 only,there is a specialconfigure pin to setthe default,Pin PCRS -down(0):Force -up(1):Force :PCRS hasinternal pull down.14Advertised flowcontrol capabilityAdvertised 100BTfull-duplex capabilityAdvertised 100BThalf-duplex capabilityAdvertised 10BTfull-duplex capability1, advertise flow control capability.0, suppress flow control capability from transmissionto link partner.1, advertise 100BT full-duplex capability.0, suppress 100BT full-duplex capability fromtransmission to link partner.1, advertise 100BT half-duplex capability.0, suppress 100BT half-duplex capability fromtransmission to link partner.1, advertise 10BT full-duplex capability.0, suppress 10BT full-duplex capability fromtransmission to link partner.R/W3R/W12R/W11R/W0M9999-12040348December 2003

元器件交易网8995MAddress0NameAdvertised 10BThalf-duplex capabilityDescription1, advertise 10BT half-duplex capability.0, suppress 10BT half-duplex capability fromtransmission to link /WDefault1MicrelRegister 29 (0x1D): Port 1 Control 13Register 45 (0x2D): Port 2 Control 13Register 61 (0x3D): Port 3 Control 13Register 77 (0x4D): Port 4 Control 13Register 93 (0x5D): Port 5 Control 13Address7NameLED offDescription1, Turn off all port’s LEDs (LEDx_2, LEDx_1, LEDx_0,where “x” is the port number). These pins will be drivenhigh if this bit is set to one.0, normal operation.1, disable port’s transmitter.0, normal operation.1, restart auto-negotiation.0, normal operation.1, disable far end fault detection and pattern transmission.0, enable far end fault detection and pattern transmission.1, power down0, normal operation1, disable auto MDI/MDIX function.0, enable auto MDI/MDIX function.1, If auto MDI/MDIX is disabled, force PHY intoMDI mode.0, Do not force PHY into MDI mode.1, Perform “local loopback,”(ie. loopback PHYs TX back to RX).0, normal /WDefault0654321TxidsRestart ANDisable Far end faultPower downDisable auto MDI/MDIXForced MDIR/W0R/WR/WR/WR/W0000R/W00LoopbackR/W0Register 30 (0x1E): Port 1 Status 0Register 46 (0x2E): Port 2 Status 0Register 62 (0x3E): Port 3 Status 0Register 78 (0x4E): Port 4 Status 0Register 94 (0x5E): Port 5 Status 0Address76543210NameMDIX statusAN doneLink goodPartner flowcontrol capabilityPartner 100BTfull-duplex capabilityPartner 100BThalf-duplex capabilityPartner 10BTfull-duplex capabilityPartner 10BThalf-duplex capabilityDescription1, MDI0, MDIX1, AN done0, AN not done1, link good0, link not good1, link partner flow control capable0, link partner not flow control capable1, link partner 100BT full-duplex capable0, link partner not 100BT full-duplex capable1, link partner 100BT half-duplex capable0, link partner not 100BT half-duplex capable1, link partner 10BT full-duplex capable0, link partner not 10BT full-duplex capable1, link partner 10BT half-duplex capable0, link partner not 10BT half-duplex capableModeRORORORORORORORODefault00000000December 200349M9999-120403

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