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2024年7月2日发(作者：)
post code（开机自检代码）
代码 bios或 3000 BIOS
00. 已显示系统的配置; 即将控制ini19引导装入..
01 处理器测试1, 处理器状态核实, 如果测试失败, 循环是无限的.
处理器寄存器的测试即将开始, 不可屏蔽中断即将停用. Cpu寄存器
测试正在进行或者失败.
02 确定诊断的类型 (正常或者制造).如果键盘缓冲器含有数据就会
失效. 停用不可屏蔽中断; 通过延迟开始. Cmos写入／读出正在进
行或者失灵.
03 清除8042键盘控制器, 发出命令 (AAH) 通电延迟已完成. Rom
bios检查部件正在进行或失灵.
04 使8042键盘控制器复位, 核实. 键盘控制器软复位／通电测试.
可编程间隔计时器的测试正在进行或失灵.
05 如果不断重复制造测试1至5, 可获得8042控制状态. 已确定软
复位／通电; 即将启动rom. Dma初如准备正在进行或者失灵.
06 使电路片作初始准备, 停用视频、奇偶性、dma电路片, 以及清
除dma电路片, 所有页面寄存器和cmos停机字节. 已启动rom计算
检查总和, 以及检查键盘缓冲器是否清除. Dma初始页面寄存器读／
写测试正在进行或失灵.
07 处理器测试2, 核实cpu寄存器的工作. 检查总和正常, 键盘缓
冲器已清除, 向键盘发出bat (基本保证测试) 命令..
08 使cmos计时器作初始准备, 正常的更新计时器的循环. 已向键
盘发出bat命令, 即将写入bat命令. Ram更新检验正在进行或失灵.
09 检查总和且必须等于零才通过. 核实键盘的基本保证测试, 接着
核实键盘命令字节. 第一个64测试正在进行.
使视频接口作初始准备 0A. 发出键盘命令字节代码, 即将写入命令
字节数据. 第一个64芯片或数据线失灵, 移位.
测试8254通道0 0B. 写入键盘控制器命令字节, 即将发出引脚23
和24的封锁／解锁命令. 第一个64奇／偶逻辑失灵.
测试8254通道1 0C. 键盘控制器引脚23、24已封锁／解锁; 已发
出nop命令. 第一个64的地址线故障.
1、检查cpu速度是否与系统时钟相匹配.2、检查控制芯片已编程值
是否符合初设置.3、视频通道测试 0D, 如果失败, 则鸣喇叭. 已处
理nop命令; 第一个64的奇偶性失灵 接着测试cmos停开寄存器.
测试cmos停机字节 0E. Cmos停开寄存器读／写测试; 将计算cmos
检查总和. 初始化输入／输出端口地址.
测试扩展的cmos 0f. 已计算cmos检查总和写入诊断字节; cmos开
始初始准备..
10 测试dma通道0. Cmos已作初始准备, cmos状态寄存器即将为日
期和时间作初始准备. 第一个64第0位故障.
11 测试dma通道1. Cmos状态寄存器已作初始准备, 即将停用dma
和中断控制器. 第一个64第1位故障.
12 测试dma页面寄存器. 停用dma控制器1以及中断控制器1和2;
即将视频显示器并使端口b作初始准备. 第一个64第2位故障.
13 测试8741键盘控制器接口. 视频显示器已停用, 端口b已作初始
准备; 即将开始电路片初始化／存储器自动检测. 第一个64第3位
故障.
14 测试存储器更新触发电路. 电路片初始化／存储器处自动检测结
束; 8254计时器测试即将开始. 第一个64第4位故障.
15 测试开头64k的系统存储器. 第2通道计时器测试了一半; 8254
第2通道计时器即将完成测试. 第一个64第5位故障.
16 establish the interrupt vector table used by 8259. Second
channel timer test ends; 8254, first channel timer is nearing
completion of testing. First 64, sixth bit faults.
17 adjust the video input / output, if equipped with video BIOS
is enabled. First channel timer test ends; 8254, zeroth channel
timer is nearing completion of testing. First 64, seventh bit
faults.
18 test video memory, if installed, select the video BIOS passed
by, and can be bypassed. The zeroth channel timer test is over;
the memory is about to start updating. First 64, eighth bit
faults.
19 test first channel interrupt controller (8259) mask bit.
Memory has been started, and memory updates will be completed.
First 64, Ninth bit faults.
1A tests second channel interrupt controllers (8259) mask bits.
Triggering the memory update line is about to check the 15
microsecond pass / break time. First 64, tenth bit faults.
1B test CMOS battery level. Complete memory update time 30
microseconds test; begin basic 64K memory test. First 64,
eleventh bit faults.
1C test CMOS check sum. First, 64, Twelfth bit faults.
1D setting CMOS configuration. First, 64, thirteenth bit
faults.
1E determines the size of the system memory and compares it to
the CMOS value. First, 64, fourteenth bit faults.
1F test 64K memory to maximum 640K. First, 64, Fifteenth bit
faults.
20 fixed 8259 section measurement. Begin the basic 64K memory
test; test the address line. The slave DMA register test is
running or malfunctioning.
21 maintain an optional interrupt (NMI) bit (parity or check
of the input / output channel). Test by address wire; is about
to trigger parity. The main DMA register test is running or
malfunctioning.
22 test 8259 interrupt function. Ending the triggering parity;
beginning the serial data read / write test. The main interrupt
mask register test is ongoing or malfunctioning.
23 test protection mode 8086 virtual mode and 8086 page mode.
The basic 64K serial data read / write test is normal; any
adjustment prior to the initialization of the interrupt vector.
Dependent interrupt interrupt memory test is in progress or out
of order.
24 measuring extended memory over 1MB. Any adjustment before
the initialization of the vector is completed and the initial
preparation of the interrupt vector is about to begin. Set the
ES segment address register to the memory high end.
25 test all memory after the first 64K. Complete interrupt
vector initial preparation. Start reading 8042 of the input /
output ports for rotational interrupts. Load interrupt vector
is in progress or malfunction.
26 exceptions to the test protection mode. Read 8042 of the
input / output port; begin to rotate the interrupt to start the
global data as an initial preparation. Open the A20 address line;
make it accessible.
27 determines the control or shielding of the cache memory RAM.
All 1 data is ready for initial completion; then any initial
preparation after the interrupt vector will be made. The
keyboard controller test is ongoing or malfunctioning.
28 determines the cache control or the special 8042 keyboard
controller. The initial preparation after the interrupt vector
is completed; the monochrome mode is about to be set. CMOS power
failure / check total calculation is in progress.
29. has been adjusted to monochrome mode, is about to adjust
the color mode. An inspection of the validity of the CMOS
configuration is under way.
2A makes the initial preparation of the keyboard controller.
Has been set to the color mode, the upcoming ROM test before
the trigger parity. Empty 64K basic memory.
2B makes initial preparations for disk drives and controllers.
Triggers the end of parity; any adjustment required before
controlling the optional video ROM check. The screen memory
test is running or malfunctioning.
2C checks the serial ports and makes them for initial
preparation. Complete the processing before the video ROM
control; check the optional video ROM and control it. Initial
screen preparation is in progress or out of order.
2D detects parallel ports,
And make it the initial preparation. Optional video ROM control
has been completed, control of any other processing will be
carried out after the video ROM restore control. The screen is
being tested to failure or flyback.
2E makes initial preparations for hard disk drives and
controllers. Processing recovery from the video ROM control;
if the EGA / VGA is not found, the display memory read / write
test is performed. Test video ROM is in progress.
2F detects the mathematical coprocessor and makes the initial
preparations. No EGA / VGA was found; upcoming display memory
read / write test. .
30 build basic memory and expand memory. Read / write test by
display memory; scan check will be done. Think the screen is
working.
31 test the selection of ROM from C800:0 to EFFF:0 and make the
initial preparation. Display memory read / write test or scan
check failed. Another display memory read / write test will be
done soon. Monochrome monitors are available.
32 programming I / O chip on COM / LTP / FDD / sound device on
mainboard, so that it is suitable for setting value. Read /
write test via another display memory, but another scan will
be performed. Color monitors (40 columns) are available for
work.
33. the video monitor will be checked and the switch will be
checked by the switch and the actual card. Color monitors (80
columns) are available for work.
34. checked display adapter; then the setting display mode. The
timer tick interrupt test is ongoing or malfunctioning.
35. complete the set display mode; the data area to be checked.
The shutdown test is ongoing or malfunctioning.
36. check the data area; the cursor that is setting the
electrifying information. The gate circuit in A20 failure.
37. cursor setting for identifying electrifying information
has been completed. Upcoming electrifying information is
displayed. Accidental interruption in protection mode.
38. complete the display of the electrifying information. The
new cursor position is about to be read out. "The RAM test is
ongoing or the address is missing.".
39. has been read to save the cursor position and is about to
display a reference string of information. .
3A. The end of the referenced string display; upcoming
Discovery & information. The interval timer channel 2 tests or
fails.
The 3B uses an OPTI circuit chip (just 486) to make an auxiliary
cache ready for the first time. "ESC > information has been
displayed; in virtual mode, memory testing is about to begin.
A daily calendar clock test is ongoing or malfunctioning.
3C creates flags that allow access to the CMOS settings. The
serial port test is running or malfunctioning.
3D initializes the keyboard / PS2 mouse / PNP device and the
total memory node. Parallel port test is in progress or out of
order.
3E attempts to open the L2 cache. The math coprocessor test is
going on or out of order.
40. has been prepared for virtual mode testing; will be checked
from video storage. Adjust the CPU speed so that it matches the
peripheral clock exactly.
The 41 interrupt has been opened and will initialize the data
to facilitate 0:0 detection, memory transformation (interrupt
controller or poor memory), recover from the video memory test,
and prepare the descriptor table. System plug-in board
selection failure.
42 display window entry. The descriptor table is ready; virtual
methods are being used for memory testing. Extended fault.
43 If the plug and play BIOS, then the serial port and parallel
port initialization. Go into virtual mode; interrupt for
diagnostics. .
44. an interrupt has been committed (for example, a diagnostic
switch has been turned on; the data is about to be initially
prepared to check the memory back at 0:0) BIOS interrupt
initialization.
45 initializes the math coprocessor. The data has been
initially prepared; the memory will be checked back at 0:0 and
the size of the system memory will be checked. .
46. the test memory has returned; the memory size has been
calculated and will be written to the page to test the memory.
Check the read-only memory ROM version.
47. is about to expand the memory write page; the basic 640K
memory will be written to the page. .
48. has written the basic memory to the page; memory to be
determined more than 1MB. Video check, CMOS reconfiguration.
49. find out the memory below 1BM and check the memory that will
be determined more than 1MB. .
4A. Find out the memory above 1MB and check it. Check the data
area. Video initialization.
4B. The test of the data area is finished. The check will be
checked < ESC > and the memory for the soft reset is more than
1MB. .
4C. Clearing memory over 1MB (soft reset) is about to clear up
memory over 1MB. .
4D
Memory that has cleared more than 1MB (soft reset). The size
of the memory will be saved. .
4E detects errors, displays error messages on the monitor, and
waits for customers to continue with the < F1 > key. Start memory
test: (no soft reset); the test of the first 64K memory is about
to appear. Display copyright information.
4F read and write soft and hard disk data for DOS boot. The size
of the memory is beginning to be tested and the memory will be
updated; serial and random memory tests will be performed. .
50 saves the CMOS value in the current BIOS monitoring time zone
to CMOS. Complete the memory test below 1MB; the size of the
high-speed memory to be re positioned and masked. Send the CPU
type and speed to the screen.
51. test the memory above 1MB. .
52 initialize all ISA read-only memory ROM, and finally assign
the IRQ number to PCI and so on. Memory tests above 1MB have
been completed; ready to be returned to the actual address.
Keyboard entry detection.
53, if not plug and play BIOS, then initialize the serial port,
parallel port and settings when the value. Save the size of the
CPU register and memory and enter the address mode. .
54. successfully open the address mode; the register that will
be saved when the device is ready to stop. Scan the hit button"
The 55. register has been restored, will disable the gate
circuit A20 address line. .
56. successfully deactivated A20 address line to check the data
area. Keyboard test is over.
57. data area checked half; continue. .
58. of the data area check is over. Will find the < < ESC > >
information. Non setting interrupt test.
59. has cleared < ESC > information; the message has been
displayed; the test of the DMA and interrupt controller is about
to begin. .
5A. Displays the settings by pressing the "F2" key.
5B. Test basic memory address.
5C. Test 640K basic memory.
60 set the hard disk boot sector virus protection function.
Testing through the DMA page register; about to test the video
memory. Test extended memory.
61 display system configuration table. The video memory check
is over; testing of the DMA 1 Basic registers is proceeding. .
62 start with interrupt 19H for system boot. Pass the test of
DMA 1 Basic register; test for DMA 2 registers. Test extended
memory address line.
63. pass the DMA 2 basic register test; check the data area. .
64. data area checked half, proceed. .
65. the data area check is over; the DMA devices 1 and 2 will
be programmed. .
The 66. DMA devices 1 and 2 are programmed to end; the 59
interrupt controller will be used as an initial preparation.
Registry configuration optimization.
67.8259 the initial preparation is over; the keyboard test is
about to begin. .
68.. Make external and internal CPU work.
6A. Tests and displays external values.
6C. Display blocked content.
6E. Displays subsidiary configuration information.
70.. The error code detected is sent to the screen display.
72.. Check the configuration for errors.
74.. Test real time clock.
76.. Scanning keyboard errors.
7A. Lock keyboard.
7C. Set the hardware interrupt vector.
7E. Does the test install the math processor?.
80. keyboard test start, clearing and checking if there is no
key stuck, the keyboard is about to resume. Turn off
programmable input / output devices.
81.
Find the error in the keyboard recovery; the stuck key is about
to issue a test command for the keyboard control port. .
82. the keyboard controller interface test is finished. The
command byte is written and the loop buffer is initially
prepared. Check and install the fixed RS232 interface (serial
port).
83. has been written to the command byte. The initial
preparation of the global data has been completed. The key is
about to be locked. .
84. check that there is no locked key. Check that the memory
is out of tune with the CMOS. Detects and installs fixed
parallel ports.
85. has checked the size of the memory; is about to display soft
error and password or bypass arrangements. .
86. check password; programming before bypass arrangement. Is
there any conflict between reopening the programmable I / O
device and detecting the fixed I / O?.
87. complete the pre arranged programming; CMOS programming
will be performed. .
88. restore the screen from the CMOS program, and continue
programming later. Initializes the BIOS data area.
89. complete the program after the program is about to display
the power screen information. .
8A. Displays the first screen information. Extended BIOS data
area initialization.
8B. This shows the message: about to block the main and video
BIOS. .
8C. Successfully blocked primary and video BIOS. It will begin
programming after CMOS, optionally programming. Initializing
floppy drive controller.
8D. Optional programming has been arranged. Then, check the
mouse and proceed with the initial preparation. .
8E. Check the mouse and complete the initial preparation. Reset
the hard disk and floppy disk. .
8F. Floppy disk has been checked. This disk will be ready for
initial use, followed by floppy disk drive. .
The 90. floppy disk configuration is finished; the existence
of the hard disk is tested. The hard disk controller is
initialized.
91. the hard disk exists, the test is over, and then the hard
disk is configured. Local bus hard disk controller
initialization.
92. hard disk configuration complete; data area to be checked.
Jump to user path 2.
93. of the data area has been checked half; continue. .
94. of the data area check, that is, set the basic and extended
memory size. Close the A20 address line.
95. adjust the size of the memory due to the type 47 mouse and
hard disk support. .
96. test shows recovery of memory; initial preparation prior
to C800:0 optional ROM control. "ES segment" registry cleaner.
97. C800:0 optional ROM control before any initial preparation
of the end, and then proceed to optional ROM inspection and
control. .
98. optional ROM control complete; any process necessary for
the optional ROM recovery control. Find ROM selection.
99. any initial preparation required after the optional ROM
test; the data zone or printer basic address that is about to
establish the timer. .
9A. Setting the timer and the printer's basic address after the
return operation; that is, set the RS - 232 basic address.
Shielding ROM selection.
9B. After returning to the initial basic RS-232 address;
coprocessor test preparation. .
9C the end of the initial preparation before the coprocessor
test, and then the coprocessor as the initial preparation.
Establish power saving management.
The 9D coprocessor prepares for initial preparation and any
initial preparation after the coprocessor test is
forthcoming. .
9E. The initial preparation after the completion of the
coprocessor will check the extended keyboard, keyboard
identifier, and digital lock. Open hardware interrupt.
9F. The extended keyboard has been checked, the identification
flag has been set, the digital lock has been turned on or off,
and a keyboard recognition command will be issued. .
A0. Issue a keyboard recognition command. The keyboard
identification flag is about to be restored. Set the time and
date.
A1. Keyboard identification flag recovery; then testing of
cache memory. .
A2. Cache memory test is over. Any soft error is about to appear.
Check the keyboard lock.
A3. Soft error display is complete. The rate of the keyboard
attack is about to set. .
A4. Tune the keyboard's hitting rate,
The waiting state of memory is about to be drawn up. Keyboard
initialization of repeated input rates.
A5. The memory waiting state is completed, and then the screen
is cleared. .
A6. The screen is cleared. The parity and non - blocking
interrupt is about to start. .
A7. Non blocking interrupts and parity are enabled. Any initial
preparation required to control optional ROM in the E000:0 is
about to take place. .
A8. Control the initial preparation of the ROM before E000:0,
and then any initial preparation required after the control of
the E000:0. Clear the "F2" key prompt.
A9. Returning from control E000:0 ROM, any initial preparation
necessary to control E000:0's optional ROM. .
AA. The initial preparation after the E000:0 controls the
optional ROM; the configuration of the system is about to be
displayed. Scan the "F2" key to hit.
AC. Go to settings
AE. Clear the self check mark of power on.
B0. Check for non critical errors.
B2. The power on self check is completed and ready to boot into
the operating system.
B4. The buzzer rings.
B6. Check password settings (optional).
B8. Clear all description tables.
BC. Clear check check values.
The default value of the BE program enters the control chip and
conforms to the modulated binary default value table. Clear
screen (optional).
BF tests CMOS build values. Detect viruses, prompt for data
backup.
C0 initializes cache. Use interrupt 19 to test and guide.
C1 memory self check. Find the "55", "AA" flag in the boot
sector.
C3 the first 256K memory test. .
C5 copies BIOS from ROM for quick self checking. .
C6 cache self check. .
CA detects cache memory (if present) and prepares it for initial
preparation. .
CB initialization redirection before keyboard batching
interrupts 13 to ROM, RAM
CC shutdown non blocking interrupt processor. .
CD sends a batch command to the keyboard controller for re
mapping input / output and memory
CE installs after the keyboard controller batch, initializes
the digital separator, and displays the information
CF writing keyboard command byte read / write function
performance test COMS
D0 interrupt handler error
D1 check & & key command
D2 disables DNA and interrupt controllers, unknown interrupt
errors
D3 initializes chipset / auto detect storage
D4 uncompressed run time code pending interrupt error
D5 unzip run time code
D6 initialization optional ROM error. (PCI) move back from an
extension block
D8 stop running error. (PCI) move back from an extension block
DA extended block move
DC stops running 10 errors
DD gives control to the RAM of the image F000:F000
E0 initialization chipset
Initialize the bridge on the E1 settings surface
Initialize the chipset E2 on the /CPU settings surface
The E3 settings surface initializes the refresh counter
Check the removable flash with the E4 settings surface
The E5 setting surface checks the half wave state of the ROM
E6 setting surface normal / performing checksum
The E7 settings surface performs a full RAM test
The E8 settings surface performs the initialization / set up
of the original device manufacturer
The E9 settings surface initializes the interrupt controller
/ multiprocessor
The EA settings surface reads the boot program code
Initialize all vectors on the EB settings surface
The EC settings surface guides the program / initialization
storage type in the flash memory
The ED settings surface initializes the boot device
Unexpected exceptions to the EE processor. Create an image of
the boot block
EF settings face test system memory
F0 initializes the interrupt vector
F1 initializes the run time clock
F2 initializes video
F3 initializes system management mode
F4 gives a "honk.""
F5 clears large segments
F6 boot to minimize the DOS operating system
F7 boot to pure DOS
F9
FF gives control of the INI19 boot loader, the motherboard OK
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