FPGA可编程逻辑器件芯片XQ7K325T-1RF900M中文规格书

2024-07-28 作者:

7Series FPGAs Data Sheet: Overview

DS180 (v2.6.1) September 8, 2020

Product Specification

General Description

Xilinx® 7series FPGAs comprise four FPGA families that address the complete range of system requirements, ranging from low cost, small form factor,

cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding

high-performance applications. The 7series FPGAs include:•

Spartan®-7 Family: Optimized for low cost, lowest power, and highI/O performance. Available in low-cost, very small form-factorpackaging for smallest PCB footprint.

Artix®-7 Family: Optimized for low power applications requiring serial

transceivers and high DSP and logic throughput. Provides the lowest

total bill of materials cost for high-throughput, cost-sensitiveapplications.

•

Kintex®-7 Family: Optimized for best price-performance with a 2Ximprovement compared to previous generation, enabling a new class of FPGAs.

Virtex®-7 Family: Optimized for highest system performance andcapacity with a 2X improvement in system performance. Highestcapability devices enabled by stacked silicon interconnect (SSI)technology.

••

Built on a state-of-the-art, high-performance, low-power (HPL), 28nm, high-k metal gate (HKMG) process technology, 7series FPGAs enable an

unparalleled increase in system performance with 2.9Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3TMAC/s DSP, while consuming 50% less power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs.

Summary of 7Series FPGA Features

••••••

Advanced high-performance FPGA logic based on real 6-input look-up table (LUT) technology configurable as distributed memory.36Kb dual-port block RAM with built-in FIFO logic for on-chip databuffering.

High-performance SelectIO™ technology with support for DDR3interfaces up to 1,866 Mb/s.

High-speed serial connectivity with built-in multi-gigabit transceiversfrom 600Mb/s to max. rates of 6.6Gb/s up to 28.05Gb/s, offering aspecial low-power mode, optimized for chip-to-chip interfaces.A user configurable analog interface (XADC), incorporating dual12-bit 1MSPS analog-to-digital converters with on-chip thermal andsupply sensors.

DSP slices with 25x18 multiplier, 48-bit accumulator, and pre-adderfor high-performance filtering, including optimized symmetriccoefficient filtering.

•••••

Powerful clock management tiles (CMT), combining phase-lockedloop (PLL) and mixed-mode clock manager (MMCM) blocks for highprecision and low jitter.

Quickly deploy embedded processing with MicroBlaze™ ated block for PCIExpress® (PCIe), for up to x8 Gen3Endpoint and Root Port designs.

Wide variety of configuration options, including support for

commodity memories, 256-bit AES encryption with HMAC/SHA-256authentication, and built-in SEU detection and correction.

Low-cost, wire-bond, bare-die flip-chip, and high signal integrity flip-chip packaging offering easy migration between family members inthe same package. All packages available in Pb-free and selectedpackages in Pb option.

Designed for high performance and lowest power with 28nm,HKMG, HPL process, 1.0V core voltage process technology and0.9V core voltage option for even lower power.

•

Table 1:7Series Families Comparison

Max. Capability

Logic CellsBlock RAM(1)DSP Slices

DSP Performance(2)MicroBlaze CPU(3)TransceiversTransceiver SpeedSerial BandwidthPCIe InterfaceMemory InterfaceI/O PinsI/O VoltagePackage OptionsNotes:

1.2.3.

Additional memory available in the form of distributed RAM.

Peak DSP performance numbers are based on symmetrical filter MicroBlaze CPU performance numbers based on microcontroller preset.

Spartan-7

102K4.2Mb160176 GMAC/s260 DMIPs

––––800Mb/s4001.2V–3.3VLow-Cost, Wire-Bond

Artix-7

215K13Mb740929GMAC/s303 DMIPs

166.6Gb/s211Gb/sx4 Gen21,066Mb/s

5001.2V–3.3VLow-Cost, Wire-Bond, Bare-Die Flip-Chip

Kintex-7

478K34Mb1,9202,845GMAC/s438 DMIPs

3212.5Gb/s800Gb/sx8 Gen21,866Mb/s

500 1.2V–3.3V

Bare-Die Flip-Chip and High-Performance Flip-Chip

Virtex-7

1,955K68Mb3,6005,335GMAC/s441 DMIPs

9628.05Gb/s2,784Gb/sx8 Gen31,866Mb/s1,2001.2V–3.3VHighest Performance

Flip-Chip

DS180 (v2.6.1) September 8, 2020Product Specification

7Series FPGAs Data Sheet: Overview

Package(1)Size (mm)Ball PitchDeviceXC7VH580TXC7VH870T

GTH24

FLG115535 x 351.0GTZ8

I/OHP(2)400

GTH48

FLG193145 x 451.0GTZ8

I/OHP(2)600

72

16

300

GTH

FLG193245 x 451.0GTZ

I/OHP(2)

DS180 (v2.6.1) September 8, 2020Product Specification

7Series FPGAs Data Sheet: Overview

•••••

High-speed SPI and BPI (parallel NOR) configurationBuilt-in MultiBoot and safe-update capability

256-bit AES encryption with HMAC/SHA-256 authenticationBuilt-in SEU detection and correctionPartial reconfiguration

Xilinx 7series FPGAs store their customized configuration in SRAM-type internal latches. There are up to 450Mb

configuration bits, depending on device size and user-design implementation options. The configuration storage is volatile

and must be reloaded whenever the FPGA is powered up. This storage can also be reloaded at any time by pulling the

PROGRAM_B pin Low. Several methods and data formats for loading configuration are available, determined by the three mode pins.

The SPI interface (x1, x2, and x4 modes) and the BPI interface (parallel-NOR x8 and x16) are two common methods used

for configuring the FPGA. Users can directly connect an SPI or BPI flash to the FPGA, and the FPGA's internal configuration

logic reads the bitstream out of the flash and configures itself. The FPGA automatically detects the bus width on the fly,

eliminating the need for any external controls or switches. Bus widths supported are x1, x2, and x4 for SPI, and x8 and x16

for BPI. The larger bus widths increase configuration speed and reduce the amount of time it takes for the FPGA to start up

after power-on. Some configuration options such as BPI are not supported in all device-package combinations. Refer to

UG470, 7 Series FPGAs Configuration User Guide for details.

In master mode, the FPGA can drive the configuration clock from an internally generated clock, or for higher speed

configuration, the FPGA can use an external configuration clock source. This allows high-speed configuration with the ease

of use characteristic of master mode. Slave modes up to 32 bits wide are also supported by the FPGA that are especially useful for processor-driven configuration.

The FPGA has the ability to reconfigure itself with a different image using SPI or BPI flash, eliminating the need for an

external controller. The FPGA can reload its original design in case there are any errors in the data transmission, ensuring

an operational FPGA at the end of the process. This is especially useful for updates to a design after the end product has

been shipped. Customers can ship their products with an early version of the design, thus getting their products to market

faster. This feature allows customers to keep their end users current with the most up-to-date designs while the product is already in the field.

The dynamic reconfiguration port (DRP) gives the system designer easy access to the configuration and status registers of

the MMCM, PLL, XADC, transceivers, and integrated block for PCI Express. The DRP behaves like a set of memory-mapped registers, accessing and modifying block-specific configuration bits as well as status and control registers.

DS180 (v2.6.1) September 8, 2020Product Specification

7Series FPGAs Data Sheet: Overview

DS180 (v2.6.1) September 8, 2020Product Specification

7Series FPGAs Data Sheet: Overview

7Series FPGA Ordering Information

Table12 shows the speed and temperature grades available in the different device families. Some devices might not be available in every speed and temperature grade.

Table 12:7 Series Speed Grade and Temperature Ranges

Device Family

Speed Grade, Temperature Range, and Operating Voltage

Devices

Commercial (C) 0°C to +85°C

-2C (1.0V)

Spartan-7

All

-1C (1.0V)

Extended (E)0°C to +100°CIndustrial (I)–40°C to +100°C

-2I (1.0V)-1I (1.0V)-1LI (0.95V)

Expanded (Q)–40°C to +125°C

-1Q (1.0V)

-3E (1.0V)

-2C (1.0V)

Artix-7

All

-1C (1.0V)

-2LE (1.0V or 0.9V)

-1I (1.0V)-1LI (0.95V)

-3E (1.0V)

XC7K70T

-2C (1.0V)

-2LE (1.0V or 0.9V)

-1C (1.0V)

XC7K160TXC7K325TXC7K355TXC7K410TXC7K420TXC7K480T

-3E (1.0V)

-2C (1.0V)

-2LE (1.0V or 0.9V)

-1C (1.0V)

-3E (1.0V)

XC7V585T

-2C (1.0V)

-2LE (1.0V)

-1C (1.0V)-2C (1.0V)

XC7V2000T

-1C (1.0V)

-3E (1.0V)

XC7VX330TXC7VX415TXC7VX485TXC7VX550TXC7VX690T

-2C (1.0V)

-2LE (1.0V)

-1C (1.0V)-2C (1.0V)

XC7VX980T

-1C (1.0V)-2C (1.0V)

XC7VX1140T

-1C (1.0V)-2C (1.0V)

Virtex-7 HT

All

-1C (1.0V)

-2GE (1.0V)-2LE (1.0V)-2GE (1.0V)-2LE (1.0V)

-1I (1.0V)

-2LE (1.0V)

-1I (1.0V)-1I (1.0V)-2I (1.0V)

-2GE (1.0V)-2LE (1.0V)

-1I (1.0V)-1I (1.0V)-2I (1.0V)-2I (1.0V)-2LI (0.95V)-1I (1.0V)-1I (1.0V)-2I (1.0V)-2I (1.0V)

Kintex-7

Virtex-7 T

Virtex-7 XT

DS180 (v2.6.1) September 8, 2020Product Specification