XC7VX690T-2FFG1927I

2024-07-28 作者:

赛灵思半导体（深圳）有限公司

DS180 (v2.6) February 27, 2018

Product Specification

General Description

7 series FPGAs comprise four FPGA families that address the complete range of system requirements, ranging from low cost, small form factor, cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding

high-performance applications. The 7 series FPGAs include:•

Spartan®-7 Family: Optimized for low cost, lowest power, and highI/O performance. Available in low-cost, very small form-factorpackaging for smallest PCB footprint.

Artix®-7 Family: Optimized for low power applications requiring serial

transceivers and high DSP and logic throughput. Provides the lowest

total bill of materials cost for high-throughput, cost-sensitiveapplications.

•

Kintex®-7 Family: Optimized for best price-performance with a 2Ximprovement compared to previous generation, enabling a new class of FPGAs.

Virtex®-7 Family: Optimized for highest system performance andcapacity with a 2X improvement in system performance. Highestcapability devices enabled by stacked silicon interconnect (SSI)technology.

••

Built on a state-of-the-art, high-performance, low-power (HPL), 28nm, high-k metal gate (HKMG) process technology, 7series FPGAs enable an

unparalleled increase in system performance with 2.9Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3TMAC/s DSP, while consuming 50% less power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs.

Summary of 7Series FPGA Features

••••••

Advanced high-performance FPGA logic based on real 6-input look-up table (LUT) technology configurable as distributed memory.36Kb dual-port block RAM with built-in FIFO logic for on-chip databuffering.

High-performance SelectIO™ technology with support for DDR3interfaces up to 1,866 Mb/s.

High-speed serial connectivity with built-in multi-gigabit transceiversfrom 600Mb/s to max. rates of 6.6Gb/s up to 28.05Gb/s, offering aspecial low-power mode, optimized for chip-to-chip interfaces.A user configurable analog interface (XADC), incorporating dual12-bit 1MSPS analog-to-digital converters with on-chip thermal andsupply sensors.

DSP slices with 25x18 multiplier, 48-bit accumulator, and pre-adderfor high-performance filtering, including optimized symmetriccoefficient filtering.

•••••

Powerful clock management tiles (CMT), combining phase-lockedloop (PLL) and mixed-mode clock manager (MMCM) blocks for highprecision and low jitter.

Quickly deploy embedded processing with MicroBlaze™ ated block for PCIExpress® (PCIe), for up to x8 Gen3Endpoint and Root Port designs.

Wide variety of configuration options, including support for

commodity memories, 256-bit AES encryption with HMAC/SHA-256authentication, and built-in SEU detection and correction.

Low-cost, wire-bond, bare-die flip-chip, and high signal integrity flip-chip packaging offering easy migration between family members inthe same package. All packages available in Pb-free and selectedpackages in Pb option.

Designed for high performance and lowest power with 28nm,HKMG, HPL process, 1.0V core voltage process technology and0.9V core voltage option for even lower power.

•

Table 1:7Series Families Comparison

Max. Capability

Logic CellsBlock RAM(1)DSP Slices

DSP Performance(2)MicroBlaze CPU(3)TransceiversTransceiver SpeedSerial BandwidthPCIe InterfaceMemory InterfaceI/O PinsI/O VoltagePackage OptionsNotes:

1.2.3.

Additional memory available in the form of distributed RAM.

Peak DSP performance numbers are based on symmetrical filter MicroBlaze CPU performance numbers based on microcontroller preset.

Spartan-7

102K4.2Mb160176 GMAC/s260 DMIPs

––––800Mb/s4001.2V–3.3VLow-Cost, Wire-Bond

Artix-7

215K13Mb740929GMAC/s303 DMIPs

166.6Gb/s211Gb/sx4 Gen21,066Mb/s

5001.2V–3.3VLow-Cost, Wire-Bond, Bare-Die Flip-Chip

Kintex-7

478K34Mb1,9202,845GMAC/s438 DMIPs

3212.5Gb/s800Gb/sx8 Gen21,866Mb/s

500 1.2V–3.3V

Bare-Die Flip-Chip and High-Performance Flip-Chip

Virtex-7

1,955K68Mb3,6005,335GMAC/s441 DMIPs

9628.05Gb/s2,784Gb/sx8 Gen31,866Mb/s1,2001.2V–3.3VHighest Performance

Flip-Chip

© Copyright 2010–2018 Xilinx, Inc., Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI Express is a trademark of PCI-SIG and used under license. All other trademarks are the property of their respective owners.

DS180 (v2.6) February 27, 2018Product Specification

7Series FPGAs Data Sheet: Overview

Spartan-7 FPGA Feature Summary

Table 2:Spartan-7 FPGA Feature Summary by Device

CLB

Device

Logic

Cells6,00012,80023,36052,16076,800102,400

Slices(1)9382,0003,6508,15012,00016,000

Max

Distributed RAM (Kb)

8321,100

DSP

Slices(2)

0160

Block RAM Blocks(3)

18Kb0240

36Kb0

Max

(Kb)1803601,6202,7003,2404,320

CMTs(4)

PCIe

GT

XADC

Blocks001111

Total I/O

Banks(5)

223588

Max User

I/O0400400

XC7S6XC7S15XC7S25XC7S50XC7S75XC7S100

223588

000000

000000

Notes:

1.2.3.4.5.

Each 7series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or DSP slice contains a pre-adder, a 25x18 multiplier, an adder, and an accumulator.

Block RAMs are fundamentally 36Kb in size; each block can also be used as two independent 18Kb CMT contains one MMCM and one not include configuration Bank 0.

DS180 (v2.6) February 27, 2018Product Specification

7Series FPGAs Data Sheet: Overview

Artix-7 FPGA Feature Summary

Table 4:Artix-7 FPGA Feature Summary by Device

Logic Cells

Configurable Logic Blocks

(CLBs)Slices(1)2,0002,6003,6505,2008,15011,80015,85033,650

Max

Distributed RAM (Kb)

06008921,1882,888

Block RAM Blocks(3)

DSP48E1

Slices(2)

18Kb0210270730

36Kb05135365

Max

(Kb)7209001,6201,8002,7003,7804,86013,140

CMTs(4)

PCIe(5)

GTPs

XADC Blocks

Total I/O

Banks(6)

Max User

I/O(7)

Device

XC7A12TXC7A15TXC7A25TXC7A35TXC7A50TXC7A75TXC7A100TXC7A200T

12,80016,64023,36033,28052,16075,520101,440215,360

180240740

353556610

11111111

244448816

11111111

353556610

00

Notes:

7series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or DSP slice contains a pre-adder, a 25x18 multiplier, an adder, and an RAMs are fundamentally 36Kb in size; each block can also be used as two independent 18Kb CMT contains one MMCM and one -7 FPGA Interface Blocks for PCI Express support up to x4 Gen not include configuration Bank number does not include GTP transceivers.

Table 5:Artix-7 FPGA Device-Package Combinations and Maximum I/Os

Package(1)Size (mm)Ball Pitch

(mm)DeviceXC7A12TXC7A15TXC7A25TXC7A35TXC7A50TXC7A75TXC7A100TXC7A200T

22

1061062

106

2

112

0000

0

GTP

(4)

CPG23610 x 100.5

I/OHR(5)

CPG23810 x 100.5

GTP

(4)

CSG32415 x 150.8

CSG32515 x 150.8

FTG25617 x 171.0

SBG48419 x 190.8

FGG484(2)23 x 231.0

FBG484(2)23 x 231.0

FGG676(3)27 x 271.0

FBG676(3)27 x 271.0

FFG115635 x 351.0

I/OHR(5)

GTP

(4)

I/OHR(5)

GTP

(4)

I/OHR(5)

GTP

(4)

I/OHR(5)

GTP

I/OHR(5)

GTP

(4)

I/OHR(5)

GTP

I/OHR(5)

GTP

(4)

I/OHR(5)

GTP

I/OHR(5)

GTP

I/OHR(5)

2112

0

210

24444

0150

0000

0

4

285

4444

5

4

285

88

300300

8

400

16

500

0

170

4

250

Notes:

packages listed are Pb-free (SBG, FBG, FFG with exemption 15). Some packages are available in Pb s in FGG484 and FBG484 are footprint compatible.

s in FGG676 and FBG676 are footprint transceivers in CP, CS, FT, and FG packages support data rates up to 6.25Gb/ = High-range I/O with support for I/O voltage from 1.2V to 3.3V.

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以赛灵思半导体（深圳）有限公司提供的参数为例，以下为XC7VX690T-2FFG1927I的详细参数，仅供参考

DS180 (v2.6) February 27, 2018Product Specification

7Series FPGAs Data Sheet: Overview

Table 11:Virtex-7 HT FPGA Device-Package Combinations and Maximum I/Os

Package(1)Size (mm)Ball PitchDeviceXC7VH580TXC7VH870T

GTH24

FLG115535 x 351.0GTZ8

I/OHP(2)400

GTH48

FLG193145 x 451.0GTZ8

I/OHP(2)600

72

16

300

GTH

FLG193245 x 451.0GTZ

I/OHP(2)

Notes:

packages listed are Pb-free with exemption 15. Some packages are available in Pb = High-performance I/O with support for I/O voltage from 1.2V to 1.8V.

DS180 (v2.6) February 27, 2018Product Specification

7Series FPGAs Data Sheet: Overview

The Spartan-7 FPGA ordering information is shown in Figure1. Refer to the Package Marking section of

UG475, 7 Series

FPGAs Packaging and Pinout for a more detailed explanation of the device markings.

Example:X C 7 S 50- 2FGGA484CDevice TypeSpeed Grade(-L1(1), -1, -2)Temperature Range C: Commercial (Tj = 0°C to +85°C) I: Industrial (Tj = –40°C to +100°C) Q: Expanded (Tj = –40°C to +125°C)Package Designator and Pin Count(Footprint Identifier)Pb-FreePackage Type1) -L1 is the ordering code for the lower power, -1L speed 180_01_012517Figure 1:Spartan-7 FPGA Ordering Information

The Artix-7, Kintex-7, and Virtex-7 FPGA ordering information, shown in Figure2, applies to all packages including Pb-Free.

Refer to the Package Marking section of

UG475, 7 Series FPGAs Packaging and Pinout for a more detailed explanation of the device markings.

Example:X C 7 K 3 2 5 T - 2 F B G 9 0 0 CDevice TypeSpeed Grade(-L1(1), -L2(2), -G2(3), -1, -2, -3)Temperature Range C: Commercial (Tj = 0°C to +85°C) E: Extended (Tj = 0°C to +100°C) I: Industrial (Tj = –40°C to +100°C)Number of Pins(4)Pb-FreeV: RoHS 6/6G (CPG, CSG, FTG, FGG): RoHS 6/6G (FFG, FBG, SBG, FLG, FHG): RoHS 6/6 with Exemption 15Package Type1) -L1 is the ordering code for the lower power, -1L speed grade.2) -L2 is the ordering code for the lower power, -2L speed grade.3) -G2 is the ordering code for the -2 speed grade devices with higher performance transceivers.4) Some package names do not exactly match the number of pins present on that package.

See UG475: 7 Series FPGAs Packaging and Pinout User Guide for package 180_01_061317Figure 2:Artix-7, Kintex-7, and Virtex-7 FPGA Ordering Information

DS180 (v2.6) February 27, 2018Product Specification