MEMORY存储芯片N25Q032A13EF840E中文规格书

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2024年6月19日发(作者：)

4Gb: x4, x8, x16 DDR3L SDRAM

Power-Down Mode

Power-Down Mode

Power-down is synchronously entered when CKE is registered LOW coincident with a

NOP or DES command. CKE is not allowed to go LOW while an MRS, MPR, ZQCAL,

READ, or WRITE operation is in progress. CKE is allowed to go LOW while any of the

other legal operations (such as ROW ACTIVATION, PRECHARGE, auto precharge, or RE-

FRESH) are in progress. However, the power-down I

DD

specifications are not applicable

until such operations have completed. Depending on the previous DRAM state and the

command issued prior to CKE going LOW, certain timing constraints must be satisfied

(as noted in Table 81). Timing diagrams detailing the different power-down mode entry

and exits are shown in Figure 98 (page 189) through Figure 107 (page 193).

Table 81: Command to Power-Down Entry Parameters

DRAM Status

Idle or active

Idle or active

Active

Active

Active

Active

Active

Idle

Power-down

Idle

Last Command Prior to

CKE LOW

1

ACTIVATE

PRECHARGE

READ or READAP

WRITE: BL8OTF, BL8MRS,

BC4OTF

WRITE: BC4MRS

WRITEAP: BL8OTF, BL8MRS,

BC4OTF

WRITEAP: BC4MRS

REFRESH

REFRESH

MODE REGISTER SET

Note:

t

REFPDEN

t

XPDLL

t

MRSPDEN

t

WRAPDEN

Parameter (Min)

t

ACTPDEN

t

PRPDEN

t

RDPDEN

t

WRPDEN

Parameter Value

1

t

CK

1

t

CK

RL + 4

t

CK + 1

t

CK

WL + 4

t

CK +

t

WR/

t

CK

WL + 2

t

CK +

t

WR/

t

CK

WL + 4

t

CK + WR + 1

t

CK

WL + 2

t

CK + WR + 1

t

CK

1

t

CK

Greater of 10

t

CK or 24ns

t

MOD

Figure

Figure 105 (page 192)

Figure 106 (page 193)

Figure 101 (page 190)

Figure 102 (page 191)

Figure 102 (page 191)

Figure 103 (page 191)

Figure 103 (page 191)

Figure 104 (page 192)

Figure 108 (page 194)

Figure 107 (page 193)

slow-exit mode precharge power-down is enabled and entered, ODT becomes asyn-

chronous

t

ANPD prior to CKE going LOW and remains asynchronous until

t

ANPD +

t

XPDLL after CKE goes HIGH.

Entering power-down disables the input and output buffers, excluding CK, CK#, ODT,

CKE, and RESET#. NOP or DES commands are required until

t

CPDED has been satis-

fied, at which time all specified input/output buffers are disabled. The DLL should be in

a locked state when power-down is entered for the fastest power-down exit timing. If

the DLL is not locked during power-down entry, the DLL must be reset after exiting

power-down mode for proper READ operation as well as synchronous ODT operation.

During power-down entry, if any bank remains open after all in-progress commands are

complete, the DRAM will be in active power-down mode. If all banks are closed after all

in-progress commands are complete, the DRAM will be in precharge power-down

mode. Precharge power-down mode must be programmed to exit with either a slow exit

mode or a fast exit mode. When entering precharge power-down mode, the DLL is

turned off in slow exit mode or kept on in fast exit mode.

The DLL also remains on when entering active power-down. ODT has special timing

constraints when slow exit mode precharge power-down is enabled and entered. Refer

to Asynchronous ODT Mode (page 210) for detailed ODT usage requirements in slow

4Gb: x4, x8, x16 DDR3L SDRAM

Electrical Specifications – DC and AC

Table 25: DDR3L 1.35V Input Switching Conditions – Command and Address

Parameter/Condition

Input high AC voltage: Logic 1

Symbol

V

IH(AC160),min

5

V

IH(AC135),min

5

V

IH(AC125),min

5

Input high DC voltage: Logic 1

Input low DC voltage: Logic 0

Input low AC voltage: Logic 0

V

IH(DC90),min

V

IL(DC90),min

V

IL(AC125),min

5

V

IL(AC135),min

5

V

IL(AC160),min

5

Input high AC voltage: Logic 1V

IH(AC160),min

5

V

IH(AC135),min

5

V

IH(AC125),min

5

Input high DC voltage: Logic 1

Input low DC voltage: Logic 0

Input low AC voltage: Logic 0

V

IH(DC90),min

V

IL(DC90),min

V

IL(AC125),min

5

V

IL(AC135),min

5

V

IL(AC160),min

5

Notes:

DDR3L-800/1066

160

135

–

90

–90

–

–135

–160

DQ and DM

160

135

–

90

–90

–

–135

–160

160

135

–

90

–90

–

–135

–160

–

135

130

90

–90

–130

–135

–

mV

mV

mV

mV

mV

mV

mV

mV

DDR3L-1333/1600

160

135

–

90

–90

–

–135

–160

DDR3L-1866/2133

–

135

125

90

–90

–125

–135

–

Units

mV

mV

mV

mV

mV

mV

mV

mV

Command and Address

voltages are referenced to V

REF

. V

REF

is V

REFCA

for control, command, and address. All

slew rates and setup/hold times are specified at the DRAM ball. V

REF

is V

REFDQ

for DQ

and DM inputs.

setup timing parameters (

t

IS and

t

DS) are referenced at V

IL(AC)

/V

IH(AC)

, not V

REF(DC)

.

hold timing parameters (

t

IH and

t

DH) are referenced at V

IL(DC)

/V

IH(DC)

, not V

REF(DC)

.

-ended input slew rate = 1 V/ns; maximum input voltage swing under test is

900mV (peak-to-peak).

two V

IH(AC)

values (and two corresponding V

IL(AC)

values) are listed for a specific

speed bin, the user may choose either value for the input AC level. Whichever value is

used, the associated setup time for that AC level must also be used. Additionally, one

V

IH(AC)

value may be used for address/command inputs and the other V

IH(AC)

value may

be used for data inputs.

For example, for DDR3-800, two input AC levels are defined: V

IH(AC160),min

and

V

IH(AC135),min

(corresponding V

IL(AC160),min

and V

IL(AC135),min

). For DDR3-800, the address/

command inputs must use either V

IH(AC160),min

with

t

IS(AC160) of 210ps or V

IH(AC150),min

with

t

IS(AC135) of 365ps; independently, the data inputs must use either V

IH(AC160),min

with

t

DS(AC160) of 75ps or V

IH(AC150),min

with

t

DS(AC150) of 125ps.

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