MEMORY存储芯片N25Q128A13BSF40中文规格书

admin管理员组

文章数量:1530914

2024年6月19日发(作者：)

4Gb: x4, x8, x16 DDR3L SDRAM

Mode Register 3 (MR3)

Figure 60: Mode Register 3 (MR3) Definition

BA2BA1BA0A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0Address bus

181716

0

1

11

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MPR MPR_RF

Mode register 3 (MR3)

M17

M16

0

0

1

1

0

1

0

1

Mode Register

Mode register set (MR0)

Mode register set 1 (MR1)

Mode register set 2 (MR2)

Mode register set 3 (MR3)

M2

0

1

MPR Enable

Normal DRAM operations

2

Dataflow from MPR

M1

M0

0

0

1

1

0

1

0

1

MPR READ Function

Predefined pattern

3

Reserved

Reserved

Reserved

Notes:

3[18 and 15:3] are reserved for future use and must all be programmed to 0.

MPR control is set for normal DRAM operation, MR3[1, 0] will be ignored.

ed to be used for READ synchronization.

MULTIPURPOSE REGISTER (MPR)

The MULTIPURPOSE REGISTER function is used to output a predefined system timing

calibration bit sequence. Bit 2 is the master bit that enables or disables access to the

MPR register, and bits 1 and 0 determine which mode the MPR is placed in. The basic

concept of the multipurpose register is shown in Figure 61 (page 153).

If MR3[2] is a 0, then the MPR access is disabled, and the DRAM operates in normal

mode. However, if MR3[2] is a 1, then the DRAM no longer outputs normal read data

but outputs MPR data as defined by MR3[0, 1]. If MR3[0, 1] is equal to 00, then a prede-

fined read pattern for system calibration is selected.

To enable the MPR, the MRS command is issued to MR3, and MR3[2] = 1. Prior to issu-

ing the MRS command, all banks must be in the idle state (all banks are precharged,

and

t

RP is met). When the MPR is enabled, any subsequent READ or RDAP commands

are redirected to the multipurpose register. The resulting operation when either a READ

or a RDAP command is issued, is defined by MR3[1:0] when the MPR is enabled (see

Table 78 (page 154)). When the MPR is enabled, only READ or RDAP commands are al-

lowed until a subsequent MRS command is issued with the MPR disabled (MR3[2] = 0).

Power-down mode, self refresh, and any other nonREAD/RDAP commands are not al-

lowed during MPR enable mode. The RESET function is supported during MPR enable

mode.

4Gb: x4, x8, x16 DDR3L SDRAM

READ Operation

t

HZ and

t

LZ transitions occur in the same access time as valid data transitions. These

parameters are referenced to a specific voltage level that specifies when the device out-

put is no longer driving

t

HZDQS and

t

HZDQ, or begins driving

t

LZDQS,

t

LZDQ. Figure

81 (page 172) shows a method of calculating the point when the device is no longer

driving

t

HZDQS and

t

HZDQ, or begins driving

t

LZDQS,

t

LZDQ, by measuring the signal

at two different voltages. The actual voltage measurement points are not critical as long

as the calculation is consistent. The parameters

t

LZDQS,

t

LZDQ,

t

HZDQS, and

t

HZDQ

are defined as single-ended.

Figure 80: Data Strobe Timing – READs

RL measured

to this point

T0

CK

CK#

t

DQSCK (MIN)

t

DQSCK (MIN)

t

DQSCK (MIN)

t

DQSCK (MIN)

t

HZDQS (MIN)

T1T2T3T4T5T6

t

LZDQS (MIN)

t

QSH

t

QSL

t

QSH

t

QSL

DQS, DQS#

early strobe

t

RPRE

t

RPST

Bit 0

t

LZDQS (MAX)

Bit 1

t

DQSCK (MAX)

Bit 2Bit 3

t

DQSCK (MAX)

Bit 4Bit 5

t

DQSCK (MAX)

Bit 6Bit 7

t

DQSCK (MAX)

t

HZDQS (MAX)

t

RPST

DQS, DQS#

late strobe

t

RPRE

t

QSH

t

QSL

t

QSH

t

QSL

Bit 0Bit 1Bit 2Bit 3Bit 4Bit 5Bit 6Bit 7

本文标签： 规格书存储芯片