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元器件交易网

TPS3307-18, TPS3307-25, TPS3307-33TRIPLE PROCESSOR SUPERVISORS

SLVS199 – DECEMBER 1998DTriple Supervisory Circuits for DSP andDDDDDDD

Processor-Based SystemsPower-On Reset Generator with FixedDelay Time of 200 ms, No ExternalCapacitor NeededTemperature-Compensated VoltageReferenceMaximum Supply Current of 40 µASupply 2Vto6VDefined RESET Output from VDD ≥ 1.1 VMSOP-8 and SO-8 –40°C to 85°CD OR DGN PACKAGE(TOP VIEW)SENSE1SENSE2SENSE3GND12348765VDDMRRESETRESETtypical applicationsFigure 1 lists some of the typical applications for the TPS3307 family, and a schematic diagram for aprocessor-based system application. This application uses TI part numbers TPS3307–33 and MSP430C325.2.5 V5 V3.3 VVDDSENSE 1SENSE 2470 kΩRESET100 nFVDDMSP430C325RESETGND••••••••Applications using DSPs, Microcontrollers

or MicroprocessorsIndustrial EquipmentProgrammable ControlsAutomotive SystemsPortable/Battery Powered EquipmentIntelligent InstrumentsWireless Communication SystemsNotebook/Desktop ComputersTPS3307–33SENSE 3620 kΩGNDFigure 1. Applications Using the TPS3307 FamilydescriptionThe TPS3307 family is a series of micropower supply voltage supervisors designed for circuit initializationprimarily in DSP and processor-based systems, which require more than one supply product spectrum of the TPS3307-xx is designed for monitoring three independent supply voltages:3.3 V/1.8 V/adj, 3.3 V/2.5 V/adj or 3.3 V/5 V/adj. The adjustable SENSE input allows the monitoring of any supplyvoltage >1.25 various supply voltage supervisors are designed to monitor the nominal supply voltage as shown in thefollowing supply voltage monitoring be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data TION DATA information is current as of publication ts conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all ght © 1998, Texas Instruments IncorporatedPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•1

元器件交易网3307-18, TPS3307-25, TPS3307-33TRIPLE PROCESSOR SUPERVISORS

SLVS199 – DECEMBER 1998

description (continued)SUPPLY VOLTAGE MONITORINGDEVICETPS3307-18TPS3307-25TPS3307-33NOMINAL SUPERVISED VOLTAGESENSE13.3 V3.3 V5 VSENSE21.8 V2.5 V3.3 VSENSE3User definedUser definedUser definedTHRESHOLD VOLTAGE (TYP)SENSE12.93 V2.93 V4.55 VSENSE21.68 V2.25 V2.93 VSENSE31.25 V†1.25 V†1.25 V††The actual sense voltage has to be adjusted by an external resistor divider according to the application power-on, RESET is asserted when the supply voltage VDD

becomes higher than 1.1 V. Thereafter, thesupply voltage supervisor monitors the SENSEn inputs

and keeps RESET active as long as SENSEn

remainbelow the threshold voltage VIT+.An internal timer delays the return of the RESET output to the inactive state (high) to ensure proper system delay time, td

typ

= 200 ms, starts after all SENSEn inputs

have risen above the threshold voltage VIT+. Whenthe voltage at any SENSE input drops below the threshold voltage VIT–, the RESET output becomes active (low) TPS3307-xx family of devices incorporates a manual reset input, MR. A low level at MR causes RESETto become active. In addition to the active-low RESET output, the TPS3307-xx family includes an active-highRESET devices are available in either 8-pin MSOP or standard 8-pin SO TPS3307-xx devices are characterized for operation over a temperature range of –40°C to 85°BLE OPTIONSPACKAGED DEVICESTASMALL OUTLINE(D)TPS3307-18D–40_C to 85_CTPS3307-25DTPS3307-33DPowerPAD™µ-SMALL OUTLINE(DGN)TPS3307-18DGNTPS3307-25DGNTPS3307-33DGNFUNCTION/TRUTH TABLESMRLHHHHHHHH†X = Don’t careSENSE1>VIT1X†00001111SENSE2>VIT2X†00110011SENSE3>VIT3X01010101RESETLLLLLLLLHRESETHHHHHHHHLMARKINGDGN PACKAGETIAAPTIAAQTIAARCHIP FORM(Y)TPS3307-18YTPS3307-25YTPS3307-33YPowerPAD is a trademark of Texas Instruments Incorporated.2POST OFFICE BOX 655303 DALLAS, TEXAS 75265•

元器件交易网

TPS3307-18, TPS3307-25, TPS3307-33TRIPLE PROCESSOR SUPERVISORS

SLVS199 – DECEMBER 1998functional block diagramVDD14 kΩMRR1SENSE 1R2R3SENSE 2R4GNDReferenceVoltageof 1.25 VSENSE 3+_+_RESETLogic + TimerRESETRESETTPS3307_+Oscillatortiming diagramSENSEnV(nom)VIT–tMR10RESET1t0tdtdtdRESET Because of SENSE Below VITRESET Because of MRRESET Because of SENSE Below VIT–tRESET Because of SENSE Below VIT–POST OFFICE BOX 655303 DALLAS, TEXAS 75265•3

元器件交易网3307-18, TPS3307-25, TPS3307-33TRIPLE PROCESSOR SUPERVISORS

SLVS199 – DECEMBER 1998

TPS3307Y chip informationThese chips, when properly assembled, display characteristics similar to those of the TPS3307. Thermalcompression or ultrasonic bonding may take place on the doped aluminium bonding pads. The chips may bemounted with conductive epoxy or a gold-silicon preform.(1)(2)(3)(4)48TPS3307Y(8)(7)(6)(5)CHIP THICKNESS: 10 TYPICALBONDING PADS: 4 × 4 MINIMUMTJ max = 150°CTOLERANCES ARE ±10%.ALL DIMENSIONS ARE IN MILS56Terminal FunctionsTERMINALNAMEGNDMRRESETRESETSENSE1SENSE2SENSE3VDDNO.47561238IOOIIII/OGroundManual resetActive-low reset outputActive-high reset outputSense voltage input 1Sense voltage input 2Sense voltage input 3Supply voltageDESCRIPTION4POST OFFICE BOX 655303 DALLAS, TEXAS 75265•

元器件交易网

TPS3307-18, TPS3307-25, TPS3307-33TRIPLE PROCESSOR SUPERVISORS

SLVS199 – DECEMBER 1998absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†Supply voltage, VDD (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VAll other pins (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 VMaximum low output current, IOL 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mAMaximum high output current, IOH –5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mAInput clamp current, IIK

(VI

< 0 or VI

> VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mAOutput clamp current, IOK (VO

< 0 or VO

> VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mAContinuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating TableOperating free-air temperature range, TA –40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°CStorage temperature range, Tstg –65Soldering temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260_C†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device 1:All voltage values are with respect to GND. For reliable operation the device must not be operated at 7 V for more than t = 1000 ATION RATING TABLEPACKAGEDGNDTA ≤ 25°CPOWER RATING2.14 mW725 mWDERATING FACTORABOVE TA = 25°C17.1 mW/°C5.8 mW/°CTA = 70°CPOWER RATING1.37 mW464 mWTA = 85°CPOWER RATING1.11 mW377 mWrecommended operating conditions at specified temperature rangeMINSupply voltage, VDDInput voltage at MR and SENSE3, VIInput voltage at SENSE1 and SENSE2, VIHigh-level input voltage at MR, VIHLow-level input voltage at MR, VILInput transition rise and fall rate at MR, ∆t/∆VOperating free-air temperature range, TA–402000.7xVDD0.3×VDD5085MAX6VDD+0.3(VDD+0.3)VIT/1.25VUNITVVVVVns/V°CPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•5

元器件交易网3307-18, TPS3307-25, TPS3307-33TRIPLE PROCESSOR SUPERVISORS

SLVS199 – DECEMBER 1998

electrical characteristics over recommended operating free-air temperature range (unlessotherwise noted)PARAMETERVOHHigh-level output voltageTEST CONDITIONSVDD = 2 V to 6 V,VDD = 3.3 V,VDD = 6 V,VDD = 2 V to 6 V,VOLLow-level output voltagePower-up reset voltage (see Note 2)VSENSE3VDD = 3.3 V,VDD = 6 V,VDD ≥1.1 V,VDD = 2 V to 6 V,TA = 0°C to 85°CIOH = –20 µAIOH = –2 mAIOH = –3 mAIOL = 20 µAIOL = 2 mAIOL = 3 mAIOL = 20 µA1.221.64VSENSE1,VSENSE2VITIT–Negative-going input threshold voltagegggg(see Note 3)VDD = 2 V to 6 V,TA = –40°C to 85°C2.202.864.46VSENSE31.221.64VSENSE1,VSENSE2VIT– = 1.25 VVIT– = 1.68 VVhysyHysteresis at VSENSEn inputVIT– = 2.25 VVIT– = 2.93 VMRIHHighlevelinputcurrentHigh-level input currentSENSE1SENSE2SENSE3ILIDDCiLowlevelinputcurrentLow-level input currentSupply currentInput capacitanceMRSENSEnVIT– = 4.55 VMR = 0.7 × VDD,VDD = 6 VVSENSE1 = VDD = 6 VVSENSE2 = VDD = 6 VVSENSE3 = VDDMR = 0 V,VSENSE1,2,3 = 0 VVDD = 6 V–1–1–4302.202.864.461.251.682.252.934.551.251.682.252.934.551015203040–13056–180891–600140µAµΑµAmVMINVDD–0.2VVDD–0.4VVDD–0.4V0.20.40.40.41.281.722.3034.641.291.732.323.024.67VVVVVTYPMAXUNITVVI = 0 V to VDD10pFNOTES: lowest supply voltage at which RESET becomes active. tr, VDD ≥15 µs/ ensure best stability of the threshold voltage, a bypass capacitor (ceramic 0.1 µF) should be placed close to the supply terminals.6POST OFFICE BOX 655303 DALLAS, TEXAS 75265•

元器件交易网

TPS3307-18, TPS3307-25, TPS3307-33TRIPLE PROCESSOR SUPERVISORS

SLVS199 – DECEMBER 1998timing requirements at VDD

= 2 V to 6 V, RL

= 1 MΩ, CL

= 50 pF, TA

= 25°CPARAMETERtwPulsewidthPulse widthSENSEnMRTEST CONDITIONSVSENSEnL = VIT– –0.2 V,VIH = 0.7 × VDD,VSENSEnH = VIT+ +0.2 VVIL = 0.3 × VDDMIN6100TYPMAXUNITµsnsswitching characteristics at VDD

= 2 V to 6 V, RL

= 1 MΩ, CL

= 50 pF, TA

= 25°CPARAMETERtdtPHLtPLHtPHLtPLHDelay timePropagation (delay) time,high-to-low level outputPropagation (delay) time,low-to-high level outputPropagation (delay) time,high-to-low level outputPropagation (delay) time,low-to-high level outputMR to RESETMR to RESETMR to RESETMR to RESETSENSEn to RESETSENSEn to RESETSENSEn to RESETSENSEn to RESETTEST CONDITIONSVI(SENSEn) ≥VIT+ + 0.2 V,MR

≥0.7 × VDD, See timing diagramVI(SENSEn) ≥VIT+ +0.2 V,VIH = 0.7 × VDD,VIL = 0.3 × VDDMIN140TYP200MAX280UNITms200500nsVIH = VIT+ +0.2 V,VIL = VITIT– –0.2 V,MR ≥0.7 × VDD15µsPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•7

元器件交易网3307-18, TPS3307-25, TPS3307-33TRIPLE PROCESSOR SUPERVISORS

SLVS199 – DECEMBER 1998

TYPICAL CHARACTERISTICSNORMALIZED SENSE THRESHOLD VOLTAGEvsFREE-AIR TEMPERATURE AT VDD1.0051.0041.003IDD–

Supply

Current

–µA1.0021.00110.9990.9980.9970.9960.995–40–15103560TA – Free-Air Temperature – °C85VDD = 2 VMR = Open6420–2–4–6–8–10–0.500.511.522.533.544.555.566.57VDD – Supply Voltage – VSENSEn = VDDMR = OpenTA = 25°CTPS3307–33Normalized

Input

Threshold

Voltage

–

VIT(TA),

VIT(25

°

C

)SUPPLY CURRENTvsSUPPLY VOLTAGEFigure 2INPUT CURRENTvsINPUT VOLTAGE AT MR1000–100II–

Input

Current

–µA–200–300–400–500–600–700–800–900–1–0.500.511.522.533.544.555.566.5VI – Input Voltage at MR – Vtw–

Minimum

Pulse

Duration

at

Vsense

–µsVDD = 6 VTA = 25°C1Figure 3MINIMUM PULSE DURATION AT SENSEvsTHRESHOLD OVERDRIVEVDD = 6 VMR = Open1001000SENSE – Threshold Overdrive – mVFigure 4Figure 58POST OFFICE BOX 655303 DALLAS, TEXAS 75265•

元器件交易网

TPS3307-18, TPS3307-25, TPS3307-33TRIPLE PROCESSOR SUPERVISORS

SLVS199 – DECEMBER 1998TYPICAL CHARACTERISTICSHIGH-LEVEL OUTPUT VOLTAGEvsHIGH-LEVEL OUTPUT CURRENT2.5VDD = 2 VMR = OpenVOH–

High-Level

Output

Voltage

–

V2VOH–

High-Level

Output

Voltage

–

V6.565.554.543.532.521.510.500–5–10–15–20–25–30–35–40–45–50IOH – High-Level Output Current – mA85°C–40°CVDD = 6 VMR = OpenHIGH-LEVEL OUTPUT VOLTAGEvsHIGH-LEVEL OUTPUT CURRENT1.5–40°C185°C0.500–0.5–1–1.5–2–2.5–3–3.5–4–4.5–5–5.5–6IOH – High-Level Output Current – mAFigure 6LOW-LEVEL OUTPUT VOLTAGEvsLOW-LEVEL OUTPUT CURRENT2.5VDD = 2 VMR = Open2VOL–

Low-Level

Output

Voltage

–

V6.565.554.543.532.521.510.5000.51.522.533.544.555.5IOL – Low-Level Output Current – mA16005Figure 7LOW-LEVEL OUTPUT VOLTAGEvsLOW-LEVEL OUTPUT CURRENTVDD = 6 VMR = OpenVOL–

Low-Level

Output

Voltage

–

V1.5185°C85°C0.5–40°C–40°C1045505560IOL – Low-Level Output Current – mAFigure 8Figure 9POST OFFICE BOX 655303 DALLAS, TEXAS 75265•9

元器件交易网3307-18, TPS3307-25, TPS3307-33TRIPLE PROCESSOR SUPERVISORS

SLVS199 – DECEMBER 1998

MECHANICAL DATAD (R-PDSO-G**)

14 PIN SHOWNPLASTIC SMALL-OUTLINE PACKAGE0.050 (1,27)0.020 (0,51)0.014 (0,35)1480.008 (0,20) NOM0.244 (6,20)0.228 (5,80)0.157 (4,00)0.150 (3,81)0.010 (0,25)MGage Plane0.010 (0,25)1A70°–8°0.044 (1,12)0.016 (0,40)Seating Plane0.069 (1,75) MAX0.010 (0,25)0.004 (0,10)0.004 (0,10)PINS **DIMA MAX80.197(5,00)0.189(4,80)140.344(8,75)0.337(8,55)160.394(10,00)0.386(9,80)4040047/D 10/96A MINNOTES: linear dimensions are in inches (millimeters).This drawing is subject to change without dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).Falls within JEDEC MS-01210POST OFFICE BOX 655303 DALLAS, TEXAS 75265•

元器件交易网

TPS3307-18, TPS3307-25, TPS3307-33TRIPLE PROCESSOR SUPERVISORS

SLVS199 – DECEMBER 1998MECHANICAL DATADGN (S-PDSO-G8)

0,380,2585PowerPAD™ PLASTIC SMALL-OUTLINE PACKAGE0,650,25MThermal Pad(See Note D)0,15 NOM3,052,954,984,78Gage Plane0,2513,052,9540°–6°0,690,41Seating Plane1,07 MAX0,150,050,104073271/A 01/98NOTES: linear dimensions are in drawing is subject to change without dimensions include mold flash or package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. This pad is electricallyand thermally connected to the backside of the die and possibly selected within JEDEC MO-187PowerPAD is a trademark of Texas Instruments OFFICE BOX 655303 DALLAS, TEXAS 75265•11

元器件交易网ORTANT NOTICETexas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinueany product or service without notice, and advise customers to obtain the latest version of relevant informationto verify, before placing orders, that information being relied on is current and complete. All products are soldsubject to the terms and conditions of sale supplied at the time of order acknowledgement, including thosepertaining to warranty, patent infringement, and limitation of warrants performance of its semiconductor products to the specifications applicable at the time of sale inaccordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extentTI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarilyperformed, except those mandated by government N APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OFDEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICALAPPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, ORWARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHERCRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TOBE FULLY AT THE CUSTOMER’S order to minimize risks associated with the customer’s applications, adequate design and operatingsafeguards must be provided by the customer to minimize inherent or procedural assumes no liability for applications assistance or customer product design. TI does not warrant or representthat any license, either express or implied, is granted under any patent right, copyright, mask work right, or otherintellectual property right of TI covering or relating to any combination, machine, or process in which suchsemiconductor products or services might be or are used. TI’s publication of information regarding any thirdparty’s products or services does not constitute TI’s approval, warranty or endorsement ght © 1998, Texas Instruments Incorporated

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